ESD protection for thin gate oxides in 65 nm. - Notermans, Guido; Smedes, Theo; Mrcarica, Zeljko; Jong, Peter C. de; Stephan, Ralph; Zwol, Hans van; Maksimovic, Dejan M. (Microelectron. Reliab., 2010)

ESD robust high-voltage active clamps. - Notermans, Guido; Quittard, Olivier; Heringa, Anco; Mrcarica, Zeljko; Blanc, Fabrice; Zwol, Hans van; Smedes, Theo; Keller, Thomas; Jong, Peter C. de (Microelectron. Reliab., 2009)

A 3-D Circuit Model to evaluate CDM performance of ICs. - Sowariraj, M. S. B.; Smedes, Theo; Jong, Peter C. de; Salm, Cora; Mouthaan, Ton J.; Kuper, Fred G. (Microelectron. Reliab., 2005)

5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. - Annema, Anne-Johan; Geelen, Govert J. G. M.; Jong, Peter C. de (IEEE J. Solid State Circuits, 2001)

5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology. - Annema, Anne-Johan; Geelen, Govert; Jong, Peter C. de (2000)