Ultra-compact silicon rings with high thermal tuning efficiency demonstrated as an 8×400 GHz WDM filter. - Deng, Qingzhong; Coster, Jeroen De; Magdziak, Rafal; El-Saeed, Ahmed H.; Elshazly, Alaa; Oktay, Mehmet; Marchese, Chiara; Lepage, Guy; Vaskasi, Javad Rahimi; Balakrishnan, Sadhishkumar; Singh, Neha; Bode, Dieter; et al. (2025)

32×100 GHz WDM filter based on ultra-compact silicon rings with a high thermal tuning efficiency of 5.85 mW/π. - Deng, Qingzhong; El-Saeed, Ahmed H.; Elshazly, Alaa; Lepage, Guy; Marchese, Chiara; Kobbi, Hakim; Magdziak, Rafal; Coster, Jeroen De; Singh, Neha; Filipcic, Marko Ersek; Croes, Kristof; Velenis, Dimitrios; et al. (2024)

Collective die-to-wafer bonding enabling low-loss evanescent coupling for optically interconnected System-on-Wafer. - Xu, Pengfei; He, Junwen; Kennes, Koen; Dvoretskii, Anton; Podpod, Arnita; Lepage, Guy; Golshani, Negin; Magdziak, Rafal; Bipul, Swetanshu; Bode, Dieter; Verheyen, Peter; Chakrabarti, Maumita; et al. (2024)

Low-loss, multi-reticle stitched SiN waveguides for 300mm wafer-level optical interconnects. - Xu, Pengfei; Marchese, Chiara; Lepage, Guy; Golshani, Negin; Eenaeme, Ruben Van; Mingardi, Andrea; Ongeval, Joost Van; Magdziak, Rafal; Halipre, Luc; Trivkovic, Darko; Verheyen, Peter; Chakrabarti, Maumita; et al. (2024)

Highly Optimized O-band Si Ring Modulators for Low-Power Hybrid CMOS-SiPho Transceivers. - Ban, Yoojin; Kim, Minkyu; Heyn, Peter De; Guermandi, Davide; Ferraro, Filippo; Rajasekaran, Natarajan; Verheyen, Peter; Bex, Pieter; He, Junwen; Kobbi, Hakim; Coster, Jeroen De; Magdziak, Rafal; et al. (2023)

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. - Lin, Hesheng; Velenis, Dimitrios; Nolmans, Philip; Sun, Xiao; Catthoor, Francky; Lauwereins, Rudy; Plas, Geert Van der; Beyne, Eric (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Efficient Backside Power Delivery for High-Performance Computing Systems. - Lin, Hesheng; Plas, Geert Van der; Sun, Xiao; Velenis, Dimitrios; Catthoor, Francky; Lauwereins, Rudy; Beyne, Eric (IEEE Trans. Very Large Scale Integr. Syst., 2022)

(Why do we need) Wireless Heterogeneous Integration (anyway?). - Peeters, Michaël; Sinha, S.; Sun, Xiao; Desset, Claude; Gramegna, Giuseppe; Slabbekoorn, John; Bex, Pieter; Pinho, Nelson; Webers, Tomas; Velenis, Dimitrios; Miller, Andy; Collaert, Nadine; et al. (2022)

110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules. - Miyaguchi, Kenichi; Ban, Yoojin; Pantano, Nicolas; Sun, Xiao; Absil, Philippe; Bogaerts, Lieve; Verheyen, Peter; Velenis, Dimitrios; Pantouvaki, Marianna; Campenhout, Joris Van (2021)

Fabrication Cost Analysis for Contactless 3-D ICs. - Papistas, Ioannis A.; Pavlidis, Vasilis F.; Velenis, Dimitrios (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Process Complexity and Cost Considerations of Multi-Layer Die Stacks. - Velenis, Dimitrios; Vos, Joeri De; Kim, Soon-Wook; Derakhshandeh, Jaber; Bex, Pieter; Capuz, Giovanni; Suhard, Samuel; Rebibis, Kenneth June; Huylenbroeck, Stefaan Van; Marinissen, Erik Jan; Phommahaxay, Alain; Miller, Andy; et al. (2019)

Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending. - Liu, Yefan; Yu, Hao; Hiblot, Gaspard; Kruv, Anastasiia; Schaekers, Marc; Horiguchi, Naoto; Velenis, Dimitrios; Wolf, Ingrid De (2019)

Processing active devices on Si interposer and impact on cost. - Velenis, Dimitrios; Detalle, Mikael; Hellings, Geert; Scholz, Mirko; Marinissen, Erik Jan; Plas, Geert Van der; Manna, Antonio La; Miller, Andy; Linten, Dimitri; Beyne, Eric (2015)

Active-lite interposer for 2.5 & 3D integration. - Hellings, Geert; Scholz, Mirko; Detalle, Mikael; Velenis, Dimitrios; Broeck, Muriel de Potter de ten; Neve, C. Roda; Li, Y.; Huylenbroeck, Stefaan Van; Chen, Shih-Hung; Marinissen, Erik Jan; Manna, Antonio La; Plas, Geert Van der; et al. (2015)

Si interposer build-up options and impact on 3D system cost. - Velenis, Dimitrios; Detalle, Mikael; Marinissen, Erik Jan; Beyne, Eric (2013)

Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique. - Stucchi, Michele; Velenis, Dimitrios; Katti, Guruprasad (IEEE Trans. Instrum. Meas., 2012)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Plas, Geert Van der; Limaye, Paresh; Loi, Igor; Mercha, Abdelkarim; Oprins, Herman; Torregiani, Cristina; Thijs, Steven; Linten, Dimitri; Stucchi, Michele; Katti, Guruprasad; Velenis, Dimitrios; Cherman, Vladimir; et al. (IEEE J. Solid State Circuits, 2011)

3D stacking using ultra thin dies. - Manna, Antonio La; Velenis, Dimitrios; Buisson, Thibault; Detalle, Mikael; Rebibis, Kenneth J.; Zhang, Wenqi; Beyne, Eric (2011)

Development of cost-effective biocompatible packaging for microelectronic devices. - Qian, Karen; Malachowski, Karl; Fiorini, Paolo; Velenis, Dimitrios; Beeck, Maaike Op de; Hoof, Chris Van (2011)

Cost effectiveness of 3D integration options. - Velenis, Dimitrios; Marinissen, Erik Jan; Beyne, Eric (2010)

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. - Verbree, Jouke; Marinissen, Erik Jan; Roussel, Philippe; Velenis, Dimitrios (2010)

3D integration: Circuit design, test, and reliability challenges. - Minas, Nikolaos; Wolf, Ingrid De; Marinissen, Erik Jan; Stucchi, Michele; Oprins, Herman; Mercha, Abdelkarim; Plas, Geert Van der; Velenis, Dimitrios; Marchal, Pol (2010)

Design issues and considerations for low-cost 3D TSV IC technology. - Plas, Geert Van der; Limaye, Paresh; Mercha, Abdelkarim; Oprins, Herman; Torregiani, Cristina; Thijs, Steven; Linten, Dimitri; Stucchi, Michele; Katti, Guruprasad; Velenis, Dimitrios; Shinichi, Domae; Cherman, Vladimir; et al. (2010)

Effects of Parameter Variations on Timing Characteristics of Clocked Registers. - Roberts, William R.; Velenis, Dimitrios (J. Circuits Syst. Comput., 2009)

Impact of 3D design choices on manufacturing cost. - Velenis, Dimitrios; Stucchi, Michele; Marinissen, Erik Jan; Swinnen, Bart; Beyne, Eric (2009)

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees. - Semerdjiev, Boyan; Velenis, Dimitrios (2007)

Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees. - Semerdjiev, Boyan; Velenis, Dimitrios (2007)

Effects of process and environmental variations on timing characteristics of clocked registers. - Roberts, William R.; Velenis, Dimitrios (2006)

Effects of crosstalk noise on H-tree clock distribution networks. - Chanodia, Itisha; Velenis, Dimitrios (2006)

Power supply variation effects on timing characteristics of clocked registers. - Roberts, William R.; Velenis, Dimitrios (2006)

Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. - Chanodia, Itisha; Velenis, Dimitrios (2006)

Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. - Roberts, William R.; Velenis, Dimitrios (2005)

Buffer sizing for delay uncertainty induced by process variations. - Velenis, Dimitrios; Sundaresha, Ramyashree; Friedman, Eby G. (2004)

Buffer Sizing for Crosstalk Induced Delay Uncertainty. - Velenis, Dimitrios; Friedman, Eby G. (2004)

Clock tree layout design for reduced delay uncertainty. - Velenis, Dimitrios; Papaefthymiou, Marios C.; Friedman, Eby G. (2004)

Reduced Delay Uncertainty in High Performance Clock Distribution Networks. - Velenis, Dimitrios; Papaefthymiou, Marios C.; Friedman, Eby G. (2003)

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. - Velenis, Dimitrios; Tang, Kevin T.; Kourtev, Ivan S.; Adler, Victor; Baez, Franklin; Friedman, Eby G. (J. Circuits Syst. Comput., 2002)

SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links. - Velenis, Dimitrios; Kalogeras, Dimitrios; Maglaris, Basil S. (2002)

Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. - Velenis, Dimitrios; Tang, Kevin T.; Kourtev, Ivan S.; Adler, Victor; Baez, Franklin; Friedman, Eby G. (2001)

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. - Velenis, Dimitrios; Friedman, Eby G.; Papaefthymiou, Marios C. (2001)