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ORCIDDimitrios Velenis
- > Home > Persons > Dimitrios Velenis
Publications
- 2022
[j7]Hesheng Lin
, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne:
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 661-665 (2022)- [j6]Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne:
Efficient Backside Power Delivery for High-Performance Computing Systems. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1748-1756 (2022) - [c28]Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, Nelson Pinho, Tomas Webers, Dimitrios Velenis, Andy Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke:
(Why do we need) Wireless Heterogeneous Integration (anyway?). VLSI Technology and Circuits 2022: 256-257 - 2019
- [c26]Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne:
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC 2019: 1-6 - 2015
- [c24]Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne:
Processing active devices on Si interposer and impact on cost. 3DIC 2015: TS11.2.1-TS11.2.4 - [c23]Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean:
Active-lite interposer for 2.5 & 3D integration. VLSIC 2015: 222- - 2013
- [c22]Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne:
Si interposer build-up options and impact on 3D system cost. 3DIC 2013: 1-5 - 2011
- [j3]Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011) - [c21]Antonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, Kenneth J. Rebibis, Wenqi Zhang, Eric Beyne:
3D stacking using ultra thin dies. 3DIC 2011: 1-5 - 2010
- [c19]Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne:
Cost effectiveness of 3D integration options. 3DIC 2010: 1-6 - [c16]Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne:
Design issues and considerations for low-cost 3D TSV IC technology. ISSCC 2010: 148-149 - 2009
- [c15]Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne:
Impact of 3D design choices on manufacturing cost. 3DIC 2009: 1-5
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