Philippe Roussel

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Praveen Raghavan

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Publications

2015
[c18]
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  dblp key:
  - conf/cicc/WeckxKRFSRLTVCG15
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  persistent URL:
  - https://dblp.org/rec/conf/cicc/WeckxKRFSRLTVCG15
Pieter Weckx, Ben Kaczer, Praveen Raghavan, Jacopo Franco, Marko Simicic, Philippe J. Roussel, Dimitri Linten, Aaron Thean, Diederik Verkest, Francky Catthoor, Guido Groeseneken:
Characterization and simulation methodology for time-dependent variability in advanced technologies. CICC 2015: 1-8
[c17]
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  dblp key:
  - conf/essderc/KaczerFWRBCDLGK15
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  persistent URL:
  - https://dblp.org/rec/conf/essderc/KaczerFWRBCDLGK15
Ben Kaczer, Jacopo Franco, Pieter Weckx, Philippe Roussel, Erik Bury, Moonju Cho, Robin Degraeve, Dimitri Linten, Guido Groeseneken, Halil Kukner, Praveen Raghavan, Francky Catthoor, Gerhard Rzepa, Wolfgang Gös, Tibor Grasser:
The defect-centric perspective of device and circuit reliability - From individual defects to circuits. ESSDERC 2015: 218-225
2014
[c9]
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  dblp key:
  - conf/essderc/BaoYRCBVBCRDRMTVTW14
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Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq:
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC 2014: 102-105

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