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ORCIDChangsik Yoo
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2020 – today
- 2024
[j45]Jinook Jung
, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. IEEE J. Solid State Circuits 59(10): 3307-3316 (2024)- [c17]Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, ChanYong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang:
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. ISSCC 2024: 242-244 - [c16]Kyeongtae Nam, Jaehyuk Kim, Dongil Lee, Kyuchang Kang, Sangyun Kim, ChangYoung Lee, Hyunchul Yoon, Donggeon Kim, Bokyeon Won, Jaejoon Song, Incheol Nam, Young-Hun Seo, Jeong-Don Ihm, Changsik Yoo, Sangjoon Hwang:
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j44]Hyeongmin Seo, Jiyun Han, Kyungmin Kim, Baek-Jin Lim, EunSeok Shin, Youngdon Choi, Hyungjong Ko, Jung-Hwan Choi, Sang-Hyun Lee, Changsik Yoo, Jaeduk Han:
A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 411-415 (2023) - [j43]Hyuntae Kim, Hyeongmin Seo, Yunseong Jo, Changsik Yoo, Jaeduk Han:
An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1301-1305 (2023) - [j42]Hyochang Kim, Hyeongmin Seo, Hyuntae Kim, Changsik Yoo, Jaeduk Han:
A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2799-2803 (2023) - [c15]Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh:
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. A-SSCC 2023: 1-4 - [c14]Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. A-SSCC 2023: 1-3 - [c13]Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee:
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. ISSCC 2023: 412-413 - [i1]Seungki Hong, Dongha Kim, Jaehyung Lee, Reum Oh, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee:
DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. CoRR abs/2302.03591 (2023) - 2022
- [c12]Dae-Hyun Kim, Byungkyu Song, Hyun-A. Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee:
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. ISSCC 2022: 448-450 - 2021
- [j41]Jeongpyo Park, Min-Gyu Jeong, Jin-Gyu Kang, Changsik Yoo:
Solar Energy-Harvesting Buck-Boost Converter With Battery-Charging and Battery-Assisted Modes. IEEE Trans. Ind. Electron. 68(3): 2163-2172 (2021) - [c11]Hojun Yoon, Wonjoo Jung, Jaewoo Park, Jindo Byun, Hyungmin Jin, Hyunyoon Cho, Youngmin Kim, Baek-Jin Lim, Young-Chul Cho, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Changsik Yoo, Sang-Hyun Lee:
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. ESSCIRC 2021: 463-466 - [c10]Seunghwan Hong, Chang-Hyun Bae, Yoo-Chang Sung, Jaewoong Kim, Junsub Yoon, Sangwoo Kim, Jin-Hyeok Baek, Cheongryong Cho, Useung Shin, Sang-Kyeom Kim, Hwan-Chul Jung, Ho-Jun Chang, Jang-Hoo Kim, Jeongsik Hwang, Hyunki Kim, Ki-Won Lee, Dongmin Kim, Han-Ki Jeong, Myung-O. Kim, Kyomin Sohn, Jeong-Don Ihm, Changsik Yoo, Sang Joon Hwang:
A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. VLSI Circuits 2021: 1-2 - 2020
- [j40]Kyungmin Kim, Changsik Yoo:
Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 415-419 (2020) - [j39]Hyochang Kim, Changsik Yoo:
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1107-1117 (2020)
2010 – 2019
- 2019
- [j38]Jin-Gyu Kang, Jeongpyo Park, Min-Gyu Jeong, Changsik Yoo:
A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range. IEEE J. Solid State Circuits 54(3): 865-873 (2019) - [j37]Donghyeok Jeong, Changsik Yoo:
A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1124-1128 (2019) - [j36]Min-Gyu Jeong, Jin-Gyu Kang, Jeongpyo Park, Changsik Yoo:
A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor. IEEE Trans. Ind. Electron. 66(11): 8445-8453 (2019) - [c9]Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo:
Time-Based Digital LDO Regualtor with Fractionally Controlled Power Transistor Strength and Fast Transient Response. A-SSCC 2019: 45-48 - 2018
- [j35]Baek-Jin Lim, Changsik Yoo:
Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation. Int. J. Circuit Theory Appl. 46(11): 2151-2159 (2018) - [c8]Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo:
A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle. ISSCC 2018: 424-426 - 2017
- [j34]Min-Ki Jeon, Won-Jun Yoo, Chan-Gyu Kim, Changsik Yoo:
A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping. IEEE Access 5: 23046-23051 (2017) - [j33]Hyochang Kim, Ook Kim, Changsik Yoo:
Duty-cycle and phase spacing error correction circuit for high-speed serial link. IEICE Electron. Express 14(12): 20170497 (2017) - [j32]Min-Ki Jeon, Changsik Yoo:
A simultaneously bidirectional inductively coupled link in a 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. 45(4): 515-529 (2017) - 2016
- [j31]Young-Jin Moon, Jeongpyo Park, Min-Gyu Jeong, Sang-Hyun Kim, Jin-Gyu Kang, Dong-Zo Kim, Changsik Yoo:
Wireless power charger for wearable medical devices with in-band communication. Int. J. Circuit Theory Appl. 44(8): 1483-1493 (2016) - [j30]Jeongpyo Park, Young-Jin Moon, Min-Gyu Jeong, Jin-Gyu Kang, Sang-Hyun Kim, Jung-Chul Gong, Changsik Yoo:
Quasi-Resonant (QR) Controller With Adaptive Switching Frequency Reduction Scheme for Flyback Converter. IEEE Trans. Ind. Electron. 63(6): 3571-3581 (2016) - [c7]Hyochang Kim, Jaewoo Park, Woosang Han, Kyuhwan Oh, Taekjun Ahn, Jun-Gi Jo, Ook Kim, Changsik Yoo:
A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology. ICCE 2016: 504-505 - 2015
- [j29]Jinho Noh, Jisoo Lee, Changsik Yoo:
An analog sigma-delta modulator with shared operational amplifier for low-power class-D audio amplifier. IEICE Electron. Express 12(17): 20150562 (2015) - [j28]Keun-Seon Ahn, Changsik Yoo:
A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process. Int. J. Circuit Theory Appl. 43(4): 544-552 (2015) - [j27]Keun-Seon Ahn, Jaewoo Park, Changsik Yoo:
A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process. Int. J. Circuit Theory Appl. 43(6): 822-828 (2015) - [j26]Younghoon Kim, Changsik Yoo:
Crosstalk cancelling voltage-mode driver for multi-Gbps parallel DRAM interface. Int. J. Circuit Theory Appl. 43(9): 1175-1182 (2015) - [j25]Young-Jin Moon, Changsik Yoo:
A switch-mode boost DC-DC converter for IR-drop compensation of charging cable. Int. J. Circuit Theory Appl. 43(10): 1391-1398 (2015) - [j24]Kyungmin Kim, Changsik Yoo:
Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1134-1138 (2015) - 2014
- [j23]Chang-Hyun Bae, Changsik Yoo:
Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples. IEICE Electron. Express 11(10): 20140274 (2014) - [j22]Dong-Ho Choi, Changsik Yoo:
A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop. IEICE Electron. Express 11(11): 20140351 (2014) - [j21]Chan-Young Jeong, Dong-Ho Choi, Changsik Yoo:
A fast automatic frequency calibration technique for a 2-6 GHz frequency synthesizer. Int. J. Circuit Theory Appl. 42(3): 309-320 (2014) - [j20]Younghoon Kim, Changsik Yoo:
A 100-kS/s 8.3-ENOB 1.7- µW Time-Domain Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 408-412 (2014) - [c6]Younghoon Kim, Min-Ki Jeon, Changsik Yoo:
Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control. ISIC 2014: 79-82 - 2013
- [j19]Jinho Noh, Dongjun Lee, Jun-Gi Jo, Changsik Yoo:
A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid. IEEE J. Solid State Circuits 48(2): 465-472 (2013) - [j18]Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo:
Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2155-2159 (2013) - 2012
- [j17]Young-Jin Moon, Yong-Seong Roh, Jung-Chul Gong, Changsik Yoo:
Load-Independent Current Control Technique of a Single-Inductor Multiple-Output Switching DC-DC converter. IEEE Trans. Circuits Syst. II Express Briefs 59-II(1): 50-54 (2012) - [j16]Jang-Woo Lee, Chang-Hyun Bae, Younghoon Kim, Changsik Yoo:
Measurement of Intersymbol Interference Jitter by Fractional Oversampling for Adaptive Equalization. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 716-720 (2012) - 2011
- [j15]Kyoohyun Lim, Sunki Min, Sang-Hoon Lee, Jaewoo Park, Kisub Kang, Hwahyeong Shin, Hyunchul Shim, Sechang Oh, Sungho Kim, Jong-Ryul Lee, Changsik Yoo, Kukjin Chun:
A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications. IEEE J. Solid State Circuits 46(7): 1648-1658 (2011) - [j14]Jun-Gi Jo, Jinho Noh, Changsik Yoo:
A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA. IEEE J. Solid State Circuits 46(11): 2469-2477 (2011) - 2010
- [j13]Ji-Hwan Seok, Jun-Gi Jo, Changsik Yoo:
A 0.6 V, 2.11 MHz, 62 dB SFDR active-RC filter in 0.13µm CMOS process. Int. J. Circuit Theory Appl. 38(1): 99-107 (2010) - [j12]Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo:
Spread spectrum clock generation for reduced electro-magnetic interference in consumer electronics devices. IEEE Trans. Consumer Electron. 56(2): 844-847 (2010) - [j11]Kyungyoul Min, Changsik Yoo:
A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport. IEEE Trans. Consumer Electron. 56(4): 2032-2036 (2010) - [c5]Kyoohyun Lim, Sunki Min, Sanghoon Lee, Jaewoo Park, Kisub Kang, Hwahyeong Shin, Hyunchul Shim, Sechang Oh, Sungho Kim, Jong-Ryul Lee, Changsik Yoo, Kukjin Chun:
A 2×2 MIMO tri-band dual-mode CMOS transceiver for worldwide WiMAX/WLAN applications. ESSCIRC 2010: 454-457
2000 – 2009
- 2009
- [j10]Young-Suk Seo, Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo, Jae-Jin Lee, Chun-Seok Jeong:
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 6-10 (2009) - 2007
- [j9]Kyungyoul Min, Changsik Yoo:
Display System Interface without Line Memory for Low-Cost System-on-Glass. IEEE Trans. Consumer Electron. 53(4): 1226-1229 (2007) - 2005
- [j8]Changsik Yoo, Kyun-Lyeol Lee:
A low-ripple poly-Si TFT charge pump for driver-integrated LCD panel. IEEE Trans. Consumer Electron. 51(2): 606-610 (2005) - [c4]Jun-Gi Jo, Changsik Yoo, Chun-Seok Jeong, Chan-Young Jeong, Mi-Young Lee, Jong-Kee Kwon:
A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology. CICC 2005: 195-198 - [c3]Jin-Hong Hwang, Mi-Young Lee, Chan-Young Jeong, Changsik Yoo:
Active-RC channel selection filter tunable from 6 kHz to 18 MHz for software-defined radio. ISCAS (5) 2005: 4803-4806 - 2004
- [j7]Changsik Yoo, Kye-Hyun Kyung, Kyunam Lim, Hi-Choon Lee, Joon-Wan Chai, Nak-Won Heo, Dong-Jin Lee, Chang-Hyun Kim:
A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. IEEE J. Solid State Circuits 39(6): 941-951 (2004) - [c2]Chun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih:
Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. ESSCIRC 2004: 379-382 - 2002
- [j6]Sungkyung Park, Changsik Yoo, Sin-Chong Park:
A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 505-507 (2002) - 2001
- [j5]Changsik Yoo, Qiuting Huang:
A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS. IEEE J. Solid State Circuits 36(5): 823-830 (2001)
1990 – 1999
- 1999
- [j4]Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo-In Cho:
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. IEEE J. Solid State Circuits 34(11): 1589-1599 (1999) - [j3]Keewook Jung, Changsik Yoo, Hyun-Kyu Yu, Wonchui Song, Wonchan Kim:
A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology. IEEE Trans. Consumer Electron. 45(1): 171-175 (1999) - 1998
- [j2]Changsik Yoo, Seung-Wook Lee, Wonchan Kim:
A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning. IEEE J. Solid State Circuits 33(1): 18-27 (1998) - [c1]Changsik Yoo, Wonchan Kim:
A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS. ASP-DAC 1998: 341-342 - 1995
- [j1]Changsik Yoo, Min-Kyu Kim, Wonchan Kim:
A static power saving TTL-to-CMOS input buffer. IEEE J. Solid State Circuits 30(5): 616-620 (1995)
Coauthor Index
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last updated on 2024-10-18 19:31 CEST by the dblp team
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