Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2col. - Nayan, Md Mizanur Rahaman; Raj, Ritik; Basha, Shaik Gouse; Krishna, Tushar; Naeemi, Azad J. (2025)

Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col. - Nayan, Md Mizanur Rahaman; Raj, Ritik; Basha, Shaik Gouse; Krishna, Tushar; Naeemi, Azad J. (CoRR, 2025)

HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing. - Nayan, Md Mizanur Rahaman; Liu, Che-Kai; Wan, Zishen; Raychowdhury, Arijit; Naeemi, Azad J. (CoRR, 2025)

Content Addressable Memory Design with Reference Resistor for Improved Search Resolution. - Narla, Siri; Koester, Steven J.; Dawley, Rebecca A.; Bol, Ageeth A.; Kumar, Piyush; Naeemi, Azad (CoRR, 2025)

WIP: Towards a Georgia Tech Semiconductor Experience for Underclassmen. - Schaffer, William L.; Rohatgi, Ajeet; Naeemi, Azad; Frazier, A. Bruno (2024)

Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search. - Narla, Siri; Kumar, Piyush; Adnaan, Mohammad; Naeemi, Azad (CoRR, 2024)

A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators. - Narla, Siri; Kumar, Piyush; Naeemi, Azad (CoRR, 2024)

Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis. - Shang, Liuting; Naeemi, Azad; Pan, Chenyun (IEEE Open J. Comput. Soc., 2023)

Roadmap for Unconventional Computing with Nanotechnology. - Finocchio, Giovanni; Bandyopadhyay, Supriyo; Lin, Peng; Pan, Gang; Yang, J. Joshua; Tomasello, Riccardo; Panagopoulos, Christos; Carpentieri, Mario; Puliafito, Vito; Åkerman, Johan; Takesue, Hiroki; Trivedi, Amit Ranjan; et al. (CoRR, 2023)

Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. - Luo, Yandong; Kumar, Piyush; Liao, Yu-Ching; Hwang, William; Xue, Fen; Tsai, Wilman; Wang, Shan X.; Naeemi, Azad; Yu, Shimeng (2022)

Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits. - Li, Hai; Nikonov, Dmitri E.; Lin, Chia-Ching; Çamsari, Kerem Yunus; Liao, Yu-Ching; Hsu, Chia-Sheng; Naeemi, Azad; Young, Ian A. (CoRR, 2021)

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). - Testa, Eleonora; Noor, Samantha Lubaba; Zografos, Odysseas; Soeken, Mathias; Catthoor, Francky; Naeemi, Azad; Micheli, Giovanni De (2020)

A Mixed Signal Architecture for Convolutional Neural Networks. - Lou, Qiuwen; Pan, Chenyun; McGuinness, John; Horváth, András; Naeemi, Azad; Niemier, Michael T.; Hu, Xiaobo Sharon (ACM J. Emerg. Technol. Comput. Syst., 2019)

Beyond Motivation and Memorization: Fostering Scientific Inquiry with Games. - Anupam, Aditya; Gupta, Shubhangi; Naeemi, Azad; Parvin, Nassim (2019)

Particle in a Box: An Experiential Environment for Learning Introductory Quantum Mechanics. - Anupam, Aditya; Gupta, Ridhima; Naeemi, Azad; Jafarinaimi, Nassim (IEEE Trans. Educ., 2018)

Hybrid piezoelectric-magnetic neurons: a proposal for energy-efficient machine learning. - Scott, William; Jeffrey, Jonathan; Heard, Blake; Nikonov, Dmitri E.; Young, Ian A.; Manipatruni, Sasikanth; Naeemi, Azad; Iraei, Rouhollah Mousavi (2018)

Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. - Prasad, Divya; Sinha, Saurabh; Cline, Brian; Moore, Steve; Naeemi, Azad (2018)

Generic system-level modeling and optimization for beyond CMOS device applications. - Huang, Victor; Pan, Chenyun; Naeemi, Azad (2018)

A mixed signal architecture for convolutional neural networks. - Lou, Qiuwen; Pan, Chenyun; McGuinness, John; Horváth, András; Naeemi, Azad; Niemier, Michael T.; Hu, Xiaobo Sharon (CoRR, 2018)

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. - Wang, Jianping; Sapatnekar, Sachin S.; Kim, Chris H.; Crowell, Paul A.; Koester, Steven J.; Datta, Supriyo; Roy, Kaushik; Raghunathan, Anand; Hu, Xiaobo Sharon; Niemier, Michael T.; Naeemi, Azad; Chien, Chia-Ling; et al. (2017)

Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. - Pan, Chenyun; Naeemi, Azad (2017)

Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications. - Pan, Chenyun; Naeemi, Azad (CoRR, 2017)

Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation. - Iraei, Rouhollah Mousavi; Kani, Nickvash; Dutta, Sourav; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Heron, John T.; Naeemi, Azad (CoRR, 2017)

Device/system performance modeling of stacked lateral NWFET logic. - Huang, Victor; Pan, Chenyun; Yakimets, Dmitry; Raghavan, Praveen; Naeemi, Azad (2016)

Performance modeling and optimization for on-chip interconnects in 3D memory arrays. - Mohseni, Javaneh; Pan, Chenyun; Naeemi, Azad (2016)

Impact of interconnect variability on circuit performance in advanced technology nodes. - Prasad, Divya; Pan, Chenyun; Naeemi, Azad (2016)

A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices. - Pan, Chenyun; Naeemi, Azad (CoRR, 2016)

Low-power Spin Valve Logic using Spin-transfer Torque with Automotion of Domain Walls. - Chang, Sou-Chi; Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.; Naeemi, Azad (CoRR, 2016)

Non-volatile spin wave majority gate at the nanoscale. - Zografos, Odysseas; Dutta, Sourav; Manfrini, Mauricio; Vaysset, Adrien; Sorée, Bart; Naeemi, Azad; Raghavan, Praveen; Lauwereins, Rudy; Radu, Iuliana P. (CoRR, 2016)

A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies. - Pan, Chenyun; Naeemi, Azad (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. - Pan, Chenyun; Raghavan, Praveen; Catthoor, Francky; Tokei, Zsolt; Naeemi, Azad (2015)

Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition. - Aghasi, Hamidreza; Iraei, Ruohollah Mousavi; Naeemi, Azad; Afshari, Ehsan (CoRR, 2015)

BEOL Scaling Limits and Next Generation Technology Prospects. - Naeemi, Azad; Ceyhan, Ahmet; Kumar, Vachan; Pan, Chenyun; Iraei, Rouhollah M.; Rakheja, Shaloo (2014)

Interactive visualizations for teaching quantum mechanics and semiconductor physics. - Peng, Rose; Dorn, Bill; Naeemi, Azad; Jafarinaimi, Nassim (2014)

Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits. - Chang, Sou-Chi; Ceyhan, Ahmet; Kumar, Vachan; Naeemi, Azad (2014)

An analytical approach to system-level variation analysis and optimization for multi-core processor. - Pan, Chenyun; Mukhopadhyay, Saibal; Naeemi, Azad (2014)

Pipeline design in spintronic circuits. - Kani, Nickvash; Naeemi, Azad (2014)

Wiring resource minimization for physically-complex Network-on-Chip architectures. - Kani, Nickvash; Naeemi, Azad (2014)

Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects. - Rakheja, Shaloo; Kumar, Vachan; Naeemi, Azad (Proc. IEEE, 2013)

System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. - Pan, Chenyun; Ceyhan, Ahmet; Naeemi, Azad (2013)

Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices. - Ceyhan, Ahmet; Naeemi, Azad (2013)

Performance modeling for interconnects for conventional and emerging switches. - Rakheja, Shaloo; Kumar, Vachan; Naeemi, Azad (2013)

System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors. - Ceyhan, Ahmet; Naeemi, Azad (2012)

System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. - Pan, Chenyun; Naeemi, Azad (2012)

Device- and system-level performance modeling for graphene P-N junction logic. - Pan, Chenyun; Naeemi, Azad (2012)

Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits. - Rakheja, Shaloo; Naeemi, Azad (2012)

Power Aware Post-manufacture Tuning of Analog Nanocircuits. - Banerjee, Aritra; Chatterjee, Subho; Naeemi, Azad; Chatterjee, Abhijit (2011)

Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling. - Rakheja, Shaloo; Naeemi, Azad (2011)

Nanoelectronics in retrospect, prospect and principle. - Meindl, James D.; Naeemi, Azad; Bakir, Muhannad S.; Murali, R. (2010)

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. - Bakir, Muhannad S.; King, Calvin; Sekar, Deepak C.; Thacker, Hiren D.; Dang, Bing; Huang, Gang; Naeemi, Azad; Meindl, James D. (2008)

Physical models for electron transport in graphene nanoribbons and their junctions. - Naeemi, Azad; Meindl, James D. (2008)

Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. - Huang, Gang; Sekar, Deepak C.; Naeemi, Azad; Shakeri, Kaveh; Meindl, James D. (2007)

Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. - Naeemi, Azad; Sarvari, Reza; Meindl, James D. (2007)

IntSim: A CAD tool for optimization of multilevel interconnect networks. - Sekar, Deepak C.; Naeemi, Azad; Sarvari, Reza; Davis, Jeffrey A.; Meindl, James D. (2007)

Carbon nanotube interconnects. - Naeemi, Azad; Meindl, James D. (2007)

Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities. - Naeemi, Azad; Bakir, Muhannad S. (2006)