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ORCIDShusuke Yoshimoto
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2020 – today
- 2024
[c26]Minon Kushihashi, Shintaro Izumi, Hirokazu Iida, Shusuke Yoshimoto, Tsuyoshi Takiuchi, Kazuya Mimura, Takeshi Kanagawa, Aiko Kakigano, Tsuyoshi Sekitani, Masayuki Endoh, Tadashi Kimura, Hiroshi Kawaguchi:
Estimation of the Stages of Labor Using a Multichannel Electrohysterogram Sensor and Conditional Variational Autoencoder. EMBC 2024: 1-4- 2022
- [j19]Shoya Matsumori
, Kosei Teramoto, Hiroya Iyori, Takanori Soda, Shusuke Yoshimoto, Haruo Mizutani:
HARU Sleep: A Deep Learning-Based Sleep Scoring System With Wearable Sheet-Type Frontal EEG Sensors. IEEE Access 10: 13624-13632 (2022) - 2020
- [j18]Ashuya Takemoto, Teppei Araki, Takafumi Uemura, Yuki Noda, Shusuke Yoshimoto, Shintaro Izumi, Shuichi Tsuruta, Tsuyoshi Sekitani:
Printable Transparent Microelectrodes toward Mechanically and Visually Imperceptible Electronics. Adv. Intell. Syst. 2(11): 2000093 (2020) - [j17]Ashuya Takemoto, Teppei Araki, Takafumi Uemura, Yuki Noda, Shusuke Yoshimoto, Shintaro Izumi, Shuichi Tsuruta, Tsuyoshi Sekitani:
Printable Transparent Microelectrodes toward Mechanically and Visually Imperceptible Electronics. Adv. Intell. Syst. 2(11): 2070105 (2020)
2010 – 2019
- 2019
- [j16]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1442-1453 (2019) - [c25]Misaki Inaoka, Shintaro Izumi, Shusuke Yoshimoto, Toshikazu Nezu, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani:
Noise Evaluation System for Biosignal Sensors Using Pseudo-Skin and Helmholtz Coil. ISMICT 2019: 1-4 - 2017
- [j15]Shusuke Yoshimoto, Teppei Araki, Takafumi Uemura, Yuki Noda, Tsuyoshi Sekitani:
Flexible electronics for bio-signal monitoring in implantable applications. IEICE Electron. Express 14(20): 20172003 (2017) - [c24]Afreen Azhari, Shusuke Yoshimoto, Toshikazu Nezu, Hirokazu Iida, Hiroki Ota, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani, Katsuyuki Morii:
A patch-type wireless forehead pulse oximeter for SpO2 measurement. BioCAS 2017: 1-4 - [c23]Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani:
Wearable pulse wave velocity sensor using flexible piezoelectric film array. BioCAS 2017: 1-4 - [c22]Fumika Tanabe, Shusuke Yoshimoto, Yuki Noda, Teppei Araki, Takafumi Uemura, Yoshinori Takeuchi, Masaharu Imai, Tsuyoshi Sekitani:
Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty. EMBC 2017: 1591-1594 - [c21]Shusuke Yoshimoto, Takafumi Uemura, Mihoko Akiyama, Yoshihiro Ihara, Satoshi Otake, Tomoharu Fujii, Teppei Araki, Tsuyoshi Sekitani:
Flexible organic TFT bio-signal amplifier using reliable chip component assembly process with conductive adhesive. EMBC 2017: 1849-1852 - 2016
- [j14]Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. IEICE Trans. Electron. 99-C(8): 901-908 (2016) - [j13]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. IPSJ Trans. Syst. LSI Des. Methodol. 9: 79-83 (2016) - [c20]Shusuke Yoshimoto, Teppei Araki, Takafumi Uemura, Toshikazu Nezu, Tsuyoshi Sekitani, Takafumi Suzuki, Fumiaki Yoshida, Masayuki Hirata:
Implantable wireless 64-channel system with flexible ECoG electrode and optogenetics probe. BioCAS 2016: 476-479 - [c19]Shusuke Yoshimoto, Teppei Araki, Takafumi Uemura, Toshikazu Nezu, Masaya Kondo, Kenichi Sasai, Masayuki Iwase, Hideki Satake, Akio Yoshida, Mitsuru Kikuchi, Tsuyoshi Sekitani:
Wireless EEG patch sensor on forehead using on-demand stretchable electrode sheet and electrode-tissue impedance scanner. EMBC 2016: 6286-6289 - [c18]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. ICECS 2016: 532-535 - 2015
- [j12]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto:
Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. IEEE Trans. Biomed. Circuits Syst. 9(5): 641-651 (2015) - [c17]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
A negative-resistance sense amplifier for low-voltage operating STT-MRAM. ASP-DAC 2015: 8-9 - [c16]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. CICC 2015: 1-4 - [c15]Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto:
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS 2015: 2904-2907 - 2014
- [j11]Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(9): 1945-1951 (2014) - [j10]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2411-2417 (2014) - [c14]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto:
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. BioCAS 2014: 280-283 - [c13]Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 6T-4C shadow memory using plate line and word line boosting. ISCAS 2014: 2736-2739 - 2013
- [j9]Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1579-1585 (2013) - [c12]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78 - [c11]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC 2013: 79-80 - [c10]Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. CICC 2013: 1-4 - 2012
- [j8]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. IEICE Electron. Express 9(6): 470-476 (2012) - [j7]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express 9(12): 1023-1029 (2012) - [j6]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. 95-C(4): 572-578 (2012) - [j5]Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi:
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Trans. Electron. 95-C(4): 579-585 (2012) - [j4]Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(8): 1359-1365 (2012) - [j3]Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Trans. Electron. 95-C(10): 1675-1681 (2012) - [j2]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2226-2233 (2012) - [c9]Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 - [c8]Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90 - [c7]Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492 - [c6]Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519 - 2011
- [j1]Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2693-2700 (2011) - [c5]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4 - [c4]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19. ESSCIRC 2011: 527-530 - [c3]Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 - 2010
- [c2]Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto:
7T SRAM enabling low-energy simultaneous block copy. CICC 2010: 1-4
2000 – 2009
- 2009
- [c1]Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663
Coauthor Index
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