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ORCIDLars Braun
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2010 – 2019
- 2013
[b1]Lars Braun:
Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems. Karlsruhe Institute of Technology, 2013, pp. 1-176- 2012
- [j3]Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker
:
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices. Int. J. Reconfigurable Comput. 2012: 219717:1-219717:10 (2012) - 2011
- [c20]Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro:
Run-time resource instantiation for fault tolerance in FPGAs. AHS 2011: 88-95 - [c19]Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker:
Development of a method for image-based motion estimation of a VTOL-MAV on FPGA. DASIP 2011: 201-208 - [c18]Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker:
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. DATE 2011: 1542-1547 - [c17]Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker:
A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker. ISCAS 2011: 853-856 - [c16]Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker:
Dynamic Processor Reconfiguration. ReConFig 2011: 123-128 - 2010
- [j2]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker:
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. ACM Trans. Reconfigurable Technol. Syst. 4(1): 4:1-4:26 (2010) - [c15]Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart:
Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. ISVLSI 2010: 190-194 - [c14]Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker:
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. ISVLSI (Selected papers) 2010: 289-302 - [c13]Lars Braun, Jürgen Becker:
Two Dimensional Dynamic Multigrained Reconfigurable Hardware. ISVLSI (Selected papers) 2010: 303-318 - [c12]Lars Braun, Jürgen Becker:
Two-Dimensional Dynamic Multigrained Reconfigurable Hardware. ISVLSI 2010: 475-476 - [c11]Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker:
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space. ReConFig 2010: 13-18 - [p1]Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker:
Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies. Dynamically Reconfigurable Systems 2010: 245-267
2000 – 2009
- 2009
- [j1]Lars Braun, Diana Göhringer, Thomas Perschke, Volker Schatz, Michael Hübner, Jürgen Becker:
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture. J. Real Time Image Process. 4(2): 109-125 (2009) - [c10]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker:
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ARC 2009: 62-73 - 2008
- [c9]Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker:
Data reallocation by exploiting FPGA configuration mechanisms. ARC 2008: 308-313 - [c8]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures. FPL 2008: 348 - [c7]Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538 - [c6]Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker:
Data path driven waveform-like reconfiguration. FPL 2008: 607-610 - [c5]Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker:
Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. IPDPS 2008: 1-6 - [c4]Alexander Klimm, Lars Braun, Jürgen Becker:
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. IPDPS 2008: 1-7 - 2007
- [c3]Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach:
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. FPL 2007: 688-691 - [c2]Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele:
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI 2007: 41-46 - 2004
- [c1]Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker:
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. FPL 2004: 1037-1041
Coauthor Index
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