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ORCIDKiyoung Choi
- > Home > Persons > Kiyoung Choi
Publications
- 2023
[i5]Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. CoRR abs/2306.15577 (2023)- 2017
- [j52]Jinho Lee
, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark Nutter, Damir A. Jamsek:
ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. Proc. VLDB Endow. 10(12): 1706-1717 (2017) - 2016
- [j46]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy. ACM Trans. Archit. Code Optim. 13(4): 34:1-34:24 (2016) - [j45]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture. IEEE Trans. Computers 65(3): 940-951 (2016) - [j44]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 453-464 (2016) - 2015
- [c100]Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
A scalable processing-in-memory accelerator for parallel graph processing. ISCA 2015: 105-117 - [c99]Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi:
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. ISCA 2015: 336-348 - 2014
- [c94]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes. DAC 2014: 139:1-139:6 - [c93]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture. HPCA 2014: 25-36 - 2013
- [c86]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. ASP-DAC 2013: 285-290 - [c84]Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Write intensity prediction for energy-efficient non-volatile caches. ISLPED 2013: 223-228 - 2012
- [j27]Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi:
Active Memory Processor for Network-on-Chip-Based Architecture. IEEE Trans. Computers 61(5): 622-635 (2012) - 2009
- [j20]Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi:
Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1034-1047 (2009) - [c59]Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi:
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. DAC 2009: 806-811 - 2008
- [c57]Dongwook Lee, Sungjoo Yoo, Kiyoung Choi:
Entry control in network-on-chip for memory power reduction. ISLPED 2008: 171-176 - 2007
- [j16]Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi:
Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Des. Autom. Embed. Syst. 11(2-3): 167-191 (2007) - [j15]Jinyong Jung, Sungjoo Yoo, Kiyoung Choi:
Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction. Des. Autom. Embed. Syst. 11(4): 223-247 (2007) - [c54]Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi:
Communication Architecture Synthesis of Cascaded Bus Matrix. ASP-DAC 2007: 171-177 - 2005
- [c46]Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Scheduler implementation in MP SoC design. ASP-DAC 2005: 151-156 - 2003
- [j11]Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae:
An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. Des. Autom. Embed. Syst. 8(2-3): 119-138 (2003) - [c40]Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh:
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. DATE 2003: 20132-20137 - [p1]Youngchul Cho, Ganghee Lee, Kiyoung Choi, Sungjoo Yoo, Nacer-Eddine Zergainoh:
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. Embedded Software for SoC 2003: 125-136 - 2002
- [c37]Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi:
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. CODES 2002: 199-204 - [c35]Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo:
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. ISLPED 2002: 84-87 - 2001
- [c31]Jinyong Jung, Sungjoo Yoo, Kiyoung Choi:
Performance improvement of multi-processor systems cosimulation based on SW analysis. DATE 2001: 749-753 - 2000
- [j5]Sungjoo Yoo, Kiyoung Choi:
Optimizing Timed Cosimulation by Hybrid Synchronization. Des. Autom. Embed. Syst. 5(2): 129-152 (2000) - [j4]Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha:
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 492-502 (2000) - [c28]Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi:
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. ASP-DAC 2000: 169-174 - [c26]Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi:
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. CODES 2000: 77-81 - [c24]Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi:
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. DATE 2000: 663-668 - 1999
- [c19]Sungjoo Yoo, Kiyoung Choi:
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. CODES 1999: 100-104 - [c16]Byungil Jeong, Sungjoo Yoo, Kiyoung Choi:
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. FPGA 1999: 247 - 1998
- [c14]Sungjoo Yoo, Kiyoung Choi:
Optimistic distributed timed cosimulation based on thread simulation model. CODES 1998: 71-75 - 1996
- [c5]Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, Kiyoung Choi:
Hardware-Software Codesign of Resource-Constrained Real-Time Systems. RTCSA 1996: 286-
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