Towards Hardware Accelerated Garbage Collection with Near-Memory Processing. - Thomas, Samuel; Choe, Jiwon; Gordon, Ofir; Petrank, Erez; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (2022)

HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. - Choe, Jiwon; Crotty, Andrew; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (2022)

Voltage Noise Mitigation With Barrier Approximation. - Chowdhury, Zamshed I.; Khatamifard, S. Karen; Zheng, Zhaoyong; Moreshet, Tali; Bahar, R. Iris; Karpuzcu, Ulya R. (IEEE Comput. Archit. Lett., 2020)

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. - Papagiannopoulou, Dimitra; Whang, Sungseob; Moreshet, Tali; Bahar, R. Iris (2019)

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. - Chowdhury, Zamshed I.; Khatamifard, S. Karen; Zheng, Zhaoyong; Moreshet, Tali; Bahar, R. Iris; Karpuzcu, Ulya R. (2019)

Attacking memory-hard scrypt with near-data-processing. - Choe, Jiwon; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2019)

Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. - Choe, Jiwon; Huang, Amy; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (2019)

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. - Papagiannopoulou, Dimitra; Marongiu, Andrea; Moreshet, Tali; Benini, Luca; Herlihy, Maurice; Bahar, R. Iris (Int. J. Parallel Program., 2018)

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. - Papagiannopoulou, Dimitra; Marongiu, Andrea; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (ACM Trans. Embed. Comput. Syst., 2017)

Evaluating critical bits in arithmetic operations due to timing violations. - Whang, Sungseob; Rachford, Tymani; Papagiannopoulou, Dimitra; Moreshet, Tali; Bahar, R. Iris (2017)

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. - Carle, Thomas; Papagiannopoulou, Dimitra; Moreshet, Tali; Marongiu, Andrea; Herlihy, Maurice; Bahar, R. Iris (2016)

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. - Papagiannopoulou, Dimitra; Capodanno, Giuseppe; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (ACM Trans. Embed. Comput. Syst., 2015)

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. - Papagiannopoulou, Dimitra; Marongiu, Andrea; Moreshet, Tali; Benini, Luca; Herlihy, Maurice; Bahar, R. Iris (2015)

Speculative synchronization for coherence-free embedded NUMA architectures. - Papagiannopoulou, Dimitra; Moreshet, Tali; Marongiu, Andrea; Benini, Luca; Herlihy, Maurice; Bahar, R. Iris (2014)

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. - Papagiannopoulou, Dimitra; Bahar, R. Iris; Moreshet, Tali; Herlihy, Maurice; Marongiu, Andrea; Benini, Luca (2013)

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. - Ferri, Cesare; Marongiu, Andrea; Lipton, Benjamin; Bahar, R. Iris; Moreshet, Tali; Benini, Luca; Herlihy, Maurice (2011)

Power-Performance Comparison of Single-Task Driven Many-Cores. - Keceli, Fuat; Moreshet, Tali; Vishkin, Uzi (2011)

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. - Ferri, Cesare; Wood, Samantha; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (J. Parallel Distributed Comput., 2010)

Thermal Management of a Many-Core Processor under Fine-Grained Parallelism. - Keceli, Fuat; Moreshet, Tali; Vishkin, Uzi (2010)

Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. - Ferri, Cesare; Wood, Samantha; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2010)

Energy efficient synchronization techniques for embedded architectures. - Ferri, Cesare; Viescas, Amber; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2008)

A hardware/software framework for supporting transactional memory in a MPSoC environment. - Ferri, Cesare; Moreshet, Tali; Bahar, R. Iris; Benini, Luca; Herlihy, Maurice (SIGARCH Comput. Archit. News, 2007)

Energy implications of multiprocessor synchronization. - Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2006)

Energy reduction in multiprocessor systems using transactional memory. - Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2005)

Effects of speculation on performance and issue queue design. - Moreshet, Tali; Bahar, R. Iris (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Power-aware issue queue design for speculative instructions. - Moreshet, Tali; Bahar, R. Iris (2003)