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ORCIDKolin Paul
- > Home > Persons > Kolin Paul
Publications
- 2021
[j26]Rajesh Kedia
, Shikha Goel, M. Balakrishnan, Kolin Paul, Rijurekha Sen:
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators. IEEE Embed. Syst. Lett. 13(3): 114-117 (2021)- 2019
- [j21]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority. J. Electron. Test. 35(5): 679-694 (2019) - [c77]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress. CODES+ISSS 2019: 12:1-12:2 - [c76]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems. DSD 2019: 4-12 - [c70]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. VLSID 2019: 464-469 - 2017
- [j18]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
Hardware acceleration of de novo genome assembly. Int. J. Embed. Syst. 9(1): 74-89 (2017) - 2015
- [j12]Arun Parakh, M. Balakrishnan, Kolin Paul:
Improving Map-Reduce for GPUs with cache. Int. J. High Perform. Syst. Archit. 5(3): 166-177 (2015) - [j10]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung:
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [c61]Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul:
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. ARC 2015: 373-382 - 2014
- [j9]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33(11): 3499-3526 (2014) - [j5]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 521-525 (2014) - [c55]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. DSD 2014: 66-73 - [c53]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array. FCCM 2014: 33 - [c48]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI 2014: 332-337 - [c46]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. VLSID 2014: 306-311 - 2013
- [c42]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
FAssem: FPGA Based Acceleration of De Novo Genome Assembly. FCCM 2013: 173-176 - [c39]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs. IPDPS Workshops 2013: 202-211 - [c34]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design 2013: 92-97 - 2012
- [c30]Arun Parakh, M. Balakrishnan, Kolin Paul:
Performance Estimation of GPUs with Cache. IPDPS Workshops 2012: 2384-2393 - 2011
- [j3]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. 7(3): 13:1-13:20 (2011) - [c27]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Architecture and tools for programmable QCA. FPT 2011: 1-4 - 2010
- [c19]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
A tiled programmable fabric using QCA. FPT 2010: 9-16 - [c18]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Clocking-Based Coplanar Wire Crossing Scheme for QCA. VLSI Design 2010: 339-344
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