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ORCIDKolin Paul
- > Home > Persons > Kolin Paul
Publications
- 2024
[c96]Avishek Choudhury, Brototi Mondal, Kolin Paul, Biplab K. Sikdar:
LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore. VLSID 2024: 690-695- 2023
- [j31]Avishek Choudhury
, Brototi Mondal, Kolin Paul, Biplab K. Sikdar:
Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor. Microprocess. Microsystems 101: 104864 (2023) - 2022
- [j29]Saurabh Tewari, Anshul Kumar, Kolin Paul:
Minimizing Off-Chip Memory Access for CNN Accelerators. IEEE Consumer Electron. Mag. 11(3): 95-104 (2022) - [c91]Saurabh Tewari, Anshul Kumar, Kolin Paul:
SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators. DATE 2022: 580-583 - 2021
- [j26]Rajesh Kedia, Shikha Goel, M. Balakrishnan, Kolin Paul, Rijurekha Sen:
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators. IEEE Embed. Syst. Lett. 13(3): 114-117 (2021) - [c88]Yu Yang, Ahmed Hemani, Kolin Paul:
Scheduling Persistent and Fully Cooperative Instructions. DSD 2021: 229-237 - [c87]Yu Yang, Ahmed Hemani, Kolin Paul:
Scheduling Persistent and Fully Cooperative Instructions. FCCM 2021: 274 - 2020
- [j22]Ahmed Hemani, Muhammad Shafique, Kolin Paul:
Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks. J. Signal Process. Syst. 92(11): 1215-1217 (2020) - [c83]Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil:
A Security Verification Template to Assess Cache Architecture Vulnerabilities. DDECS 2020: 1-6 - [c80]Ameer Shalabi, Kolin Paul, Tara Ghasempouri, Jaan Raik:
NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad. ISVLSI 2020: 54-59 - [c79]Saurabh Tewari, Anshul Kumar, Kolin Paul:
Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators. ISVLSI 2020: 240-245 - [c78]Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul:
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. VLSI-SOC 2020: 16-21 - [i3]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. CoRR abs/2002.11108 (2020) - [i2]Sourav Das, Samuel Wedaj, Kolin Paul, Umesh Bellur, Vinay Joseph Ribeiro:
Airmed: Efficient Self-Healing Network of Low-End Devices. CoRR abs/2004.12442 (2020) - [i1]Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul:
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. CoRR abs/2008.08409 (2020) - 2019
- [j21]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority. J. Electron. Test. 35(5): 679-694 (2019) - [j20]Samuel Wedaj, Kolin Paul, Vinay J. Ribeiro:
DADS: Decentralized Attestation for Device Swarms. ACM Trans. Priv. Secur. 22(3): 19:1-19:29 (2019) - [c77]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress. CODES+ISSS 2019: 12:1-12:2 - [c76]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems. DSD 2019: 4-12 - [c72]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. IOLTS 2019: 239-242 - [c71]Dimitrios Stathis, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred G. Grabherr, Rafi Ahmad:
Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. ISVLSI 2019: 560-567 - [c70]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. VLSID 2019: 464-469 - 2018
- [c68]Yu Yang, Dimitrios Stathis, Prashant Sharma, Kolin Paul, Ahmed Hemani, Manfred G. Grabherr, Rafi Ahmad:
RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. SAMOS 2018: 105-114 - 2017
- [j18]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
Hardware acceleration of de novo genome assembly. Int. J. Embed. Syst. 9(1): 74-89 (2017) - [j17]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. Int. J. Parallel Program. 45(6): 1420-1460 (2017) - [j15]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. J. Signal Process. Syst. 87(3): 327-341 (2017) - [c66]Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Kolin Paul, Naeem Abbas:
MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks. IPDPS 2017: 276-286 - 2016
- [j13]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen:
Polymorphic Configuration Architecture for CGRAs. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 403-407 (2016) - 2015
- [j12]Arun Parakh, M. Balakrishnan, Kolin Paul:
Improving Map-Reduce for GPUs with cache. Int. J. High Perform. Syst. Archit. 5(3): 166-177 (2015) - [j11]Syed M. A. H. Jafri, Ozan Ozbag, Nasim Farahini, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs. ACM J. Emerg. Technol. Comput. Syst. 11(4): 40:1-40:29 (2015) - [j10]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung:
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [c61]Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul:
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. ARC 2015: 373-382 - [c59]Pei Liu, Ahmed Hemani, Kolin Paul:
3D-stacked many-core architecture for biological sequence analysis problems. SAMOS 2015: 211-220 - 2014
- [j9]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33(11): 3499-3526 (2014) - [j8]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18(3-4): 295-327 (2014) - [j6]Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul:
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. Microprocess. Microsystems 38(8): 788-802 (2014) - [j5]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 521-525 (2014) - [c56]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Morphable Compression Architecture for Efficient Configuration in CGRAs. DSD 2014: 42-49 - [c55]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. DSD 2014: 66-73 - [c54]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Customizable Compression Architecture for Efficient Configuration in CGRAs. FCCM 2014: 31 - [c53]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array. FCCM 2014: 33 - [c52]Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
TransPar: Transformation based dynamic Parallelism for low power CGRAs. FPL 2014: 1-8 - [c49]Pei Liu, Ahmed Hemani, Kolin Paul:
A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture. ISSoC 2014: 1-8 - [c48]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI 2014: 332-337 - [c47]Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. ICSAMOS 2014: 233-241 - [c46]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. VLSID 2014: 306-311 - 2013
- [j4]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. Microprocess. Microsystems 37(8-A): 811-822 (2013) - [c44]Nasim Farahini, Ahmed Hemani, Kolin Paul:
Distributed Runtime Computation of Constraints for Multiple Inner Loops. DSD 2013: 389-395 - [c43]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD 2013: 525-534 - [c42]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
FAssem: FPGA Based Acceleration of De Novo Genome Assembly. FCCM 2013: 173-176 - [c41]Ashutosh Jain, Anshuj Garg, Kolin Paul:
GAGM: Genome assembly on GPU using mate pairs. HiPC 2013: 176-185 - [c40]Anshuj Garg, Ashutosh Jain, Kolin Paul:
GGAKE: GPU Based Genome Assembly Using K-Mer Extension. HPCC/EUC 2013: 1105-1112 - [c39]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs. IPDPS Workshops 2013: 202-211 - [c38]U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar:
High performance 3D-FFT implementation. ISCAS 2013: 2227-2230 - [c37]Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. ISQED 2013: 104-111 - [c36]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC 2013: 1-8 - [c35]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs. ICSAMOS 2013: 104-112 - [c34]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design 2013: 92-97 - 2012
- [c33]Kolin Paul, Chinmaya Dash, Mansureh Shahraki Moghaddam:
reMORPH: A Runtime Reconfigurable Architecture. DSD 2012: 26-33 - [c32]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. DSD 2012: 242-249 - [c31]Pei Liu, Ahmed Hemani, Kolin Paul:
Improved Bioinformatics Processing Unit for Multiple Applications. IPDPS Workshops 2012: 390-396 - [c30]Arun Parakh, M. Balakrishnan, Kolin Paul:
Performance Estimation of GPUs with Cache. IPDPS Workshops 2012: 2384-2393 - [c28]Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen:
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS 2012: 450-458 - 2011
- [j3]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. 7(3): 13:1-13:20 (2011) - [c27]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Architecture and tools for programmable QCA. FPT 2011: 1-4 - [c26]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. FPT 2011: 1-6 - [c25]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures. IPDPS Workshops 2011: 290-293 - [c24]Pei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul:
A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics. ReConFig 2011: 190-197 - [c23]Pei Liu, Ahmed Hemani, Kolin Paul:
A Reconfigurable Processor for Phylogenetic Inference. VLSI Design 2011: 226-231 - 2010
- [c20]Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712 - [c19]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
A tiled programmable fabric using QCA. FPT 2010: 9-16 - [c18]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Clocking-Based Coplanar Wire Crossing Scheme for QCA. VLSI Design 2010: 339-344 - 2008
- [c17]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. VLSI Design 2008: 261-266 - [c16]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. VLSI Design 2008: 348-353 - 2007
- [c15]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Recurring Pattern Identification and its Application to Instruction Set Extension. CDES 2007: 67-73 - [c13]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Application Specific Datapath Extension with Distributed I/O Functional Units. VLSI Design 2007: 551-558 - 2005
- [c10]Sanjay V. Rajopadhye, Kolin Paul:
A 1.5-D Architecture for Back-Propagation Training. ERSA 2005: 112-118 - 2002
- [j1]Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri:
Theory of Extended Linear Machines. IEEE Trans. Computers 51(9): 1106-1110 (2002) - 2000
- [c8]Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar:
Theory and Applications of Cellular Automata for VLSI Design and Testing. VLSI Design 2000: 4 - [c7]Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury:
GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. VLSI Design 2000: 140-143 - [c6]Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury:
Scalable Pipelined Micro-Architecture for Wavelet Transform. VLSI Design 2000: 144- - [c5]Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee:
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. VLSI Design 2000: 556-561 - [c4]Kolin Paul, Dipanwita Roy Chowdhury:
Application of GF(2p) CA in Burst Error Correcting Codes. VLSI Design 2000: 562-567 - 1999
- [c3]Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri:
Cellular Automata Based Transform Coding for Image Compression. HiPC 1999: 269-273 - [c2]Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri:
A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. VLSI Design 1999: 532-537 - 1998
- [c1]Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri:
Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. Asian Test Symposium 1998: 388-
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