BibTeX records: Bob Verbruggen

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@inproceedings{DBLP:conf/isscc/KeaneHV21,
  author       = {John Keane and
                  Chih{-}Cheng Hsieh and
                  Bob Verbruggen},
  title        = {Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
                  San Francisco, CA, USA, February 13-22, 2021},
  pages        = {368--369},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISSCC42613.2021.9366055},
  doi          = {10.1109/ISSCC42613.2021.9366055},
  timestamp    = {Wed, 10 Mar 2021 15:02:58 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/KeaneHV21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ChaeWVHL19,
  author       = {Youngcheol Chae and
                  Bernhard Wicht and
                  Bob Verbruggen and
                  Payam Heydari and
                  Howard C. Luong},
  title        = {Introduction to the Special Issue on the 2019 {IEEE} International
                  Solid-State Circuits Conference {(ISSCC)}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {12},
  pages        = {3243--3246},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2019.2946496},
  doi          = {10.1109/JSSC.2019.2946496},
  timestamp    = {Mon, 26 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ChaeWVHL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TurkerBUVCMEFFC18,
  author       = {Didem Turker and
                  Ade Bekele and
                  Parag Upadhyaya and
                  Bob Verbruggen and
                  Ying Cao and
                  Shaojun Ma and
                  Christophe Erdmann and
                  Brendan Farley and
                  Yohan Frans and
                  Ken Chang},
  title        = {A 7.4-to-14GHz {PLL} with 54fsrms jitter in 16nm FinFET for integrated
                  RF-data-converter SoCs},
  booktitle    = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2018, San Francisco, CA, USA, February 11-15, 2018},
  pages        = {378--380},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ISSCC.2018.8310342},
  doi          = {10.1109/ISSCC.2018.8310342},
  timestamp    = {Mon, 26 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TurkerBUVCMEFFC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/VazVECMBCWMMLPT18,
  author       = {Bruno Vaz and
                  Bob Verbruggen and
                  Christophe Erdmann and
                  Diarmuid Collins and
                  John McGrath and
                  Ali Boumaalif and
                  Edward Cullen and
                  Darragh Walsh and
                  Alonso Morgado and
                  Conrado Mesadri and
                  Brian Long and
                  Rajitha Pathepuram and
                  Ronnie De La Torre and
                  Alvin Manlapat and
                  Georgios Karyotis and
                  Dimitris Tsaliagos and
                  Patrick Lynch and
                  Peng Lim and
                  Daire Breathnach and
                  Brendan Farley},
  title        = {A 13Bit 5GS/S {ADC} with Time-Interleaved Chopping Calibration in
                  16NM FinFET},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {99--100},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502306},
  doi          = {10.1109/VLSIC.2018.8502306},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/VazVECMBCWMMLPT18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/ErdmannVVPMKTOL18,
  author       = {Christophe Erdmann and
                  Bob Verbruggen and
                  Bruno Vaz and
                  Roberto Pelliconi and
                  John McGrath and
                  Ryan Kinnerk and
                  Ronnie De La Torre and
                  John O'Dwyer and
                  Patrick Lynch and
                  Padraig Kelly and
                  Peng Lim and
                  Daire Breathnach and
                  Brendan Farley},
  title        = {A modular 16NM Direct-RF {TX/RX} Embedding 9GS/S {DAC} and 4.5GS/S
                  {ADC} with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic
                  Integration in 5G Base-Station SoC},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {219--220},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502292},
  doi          = {10.1109/VLSIC.2018.8502292},
  timestamp    = {Tue, 30 Oct 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsic/ErdmannVVPMKTOL18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/FarleyEVMCVPBLB17,
  author       = {Brendan Farley and
                  Christophe Erdmann and
                  Bruno Vaz and
                  John McGrath and
                  Edward Cullen and
                  Bob Verbruggen and
                  Roberto Pelliconi and
                  Daire Breathnach and
                  Peng Lim and
                  Ali Boumaalif and
                  Patrick Lynch and
                  Conrado Mesadri and
                  David Melinn and
                  Kwee Peng Yap and
                  Liam Madden},
  title        = {A programmable RFSoC in 16nm FinFET technology for wideband communications},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
                  Korea (South), November 6-8, 2017},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ASSCC.2017.8240201},
  doi          = {10.1109/ASSCC.2017.8240201},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/FarleyEVMCVPBLB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/VazLVLMBMKTMBEF17,
  author       = {Bruno Vaz and
                  Adrian Lynam and
                  Bob Verbruggen and
                  Asma Laraba and
                  Conrado Mesadri and
                  Ali Boumaalif and
                  John McGrath and
                  Umanath Kamath and
                  Ronnie De La Torre and
                  Alvin Manlapat and
                  Daire Breathnach and
                  Christophe Erdmann and
                  Brendan Farley},
  title        = {16.1 {A} 13b 4GS/s digitally assisted dynamic 3-stage asynchronous
                  pipelined-SAR {ADC}},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {276--277},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870368},
  doi          = {10.1109/ISSCC.2017.7870368},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/VazLVLMBMKTMBEF17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ErdmannCBPVMCTG17,
  author       = {Christophe Erdmann and
                  Edward Cullen and
                  Damien Brouard and
                  Roberto Pelliconi and
                  Bob Verbruggen and
                  John McGrath and
                  Diarmuid Collins and
                  Marites De La Torre and
                  Pierrick Gay and
                  Patrick Lynch and
                  Peng Lim and
                  Anthony Collins and
                  Brendan Farley},
  title        = {16.3 {A} 330mW 14b 6.8GS/s dual-mode {RF} {DAC} in 16nm FinFET achieving
                  -70.8dBc {ACPR} in a 20MHz channel at 5.2GHz},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {280--281},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870370},
  doi          = {10.1109/ISSCC.2017.7870370},
  timestamp    = {Wed, 17 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ErdmannCBPVMCTG17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LeeVM17,
  author       = {Tai{-}Cheng Lee and
                  Bob Verbruggen and
                  Un{-}Ku Moon},
  title        = {Session 28 overview: Hybrid ADCs},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {464--465},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870462},
  doi          = {10.1109/ISSCC.2017.7870462},
  timestamp    = {Wed, 17 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeVM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KhalafVVLMSLVIB16,
  author       = {Khaled Khalaf and
                  Vojkan Vidojkovic and
                  Kristof Vaesen and
                  Michael Libois and
                  Giovanni Mangraviti and
                  Viki Szortyka and
                  Chunshu Li and
                  Bob Verbruggen and
                  Mark Ingels and
                  Andr{\'{e}} Bourdoux and
                  Charlotte Soens and
                  Wim Van Thillo and
                  John R. Long and
                  Piet Wambacq},
  title        = {Digitally Modulated {CMOS} Polar Transmitters for Highly-Efficient
                  mm-Wave Wireless Communication},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {51},
  number       = {7},
  pages        = {1579--1592},
  year         = {2016},
  url          = {https://doi.org/10.1109/JSSC.2016.2544784},
  doi          = {10.1109/JSSC.2016.2544784},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KhalafVVLMSLVIB16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/MalkiVMWC16,
  author       = {Badr Malki and
                  Bob Verbruggen and
                  Ewout Martens and
                  Piet Wambacq and
                  Jan Craninckx},
  title        = {A 150 kHz-80 MHz {BW} Discrete-Time Analog Baseband for Software-Defined-Radio
                  Receivers using a 5th-Order {IIR} LPF, Active {FIR} and a 10 bit 300
                  MS/s {ADC} in 28 nm {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {51},
  number       = {7},
  pages        = {1593--1606},
  year         = {2016},
  url          = {https://doi.org/10.1109/JSSC.2016.2561979},
  doi          = {10.1109/JSSC.2016.2561979},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/MalkiVMWC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/MalkiYVWC15,
  author       = {Badr Malki and
                  Takaya Yamamoto and
                  Bob Verbruggen and
                  Piet Wambacq and
                  Jan Craninckx},
  title        = {Correction to "A 70 dB {DR} 10 b 0-to-80 MS/s Current-Integrating
                  {SAR} {ADC} With Adaptive Dynamic Range"},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {50},
  number       = {2},
  pages        = {619},
  year         = {2015},
  url          = {https://doi.org/10.1109/JSSC.2014.2388331},
  doi          = {10.1109/JSSC.2014.2388331},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/MalkiYVWC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/VerbruggenTYIMC15,
  author       = {Bob Verbruggen and
                  Jorgo Tsouhlarakis and
                  Takaya Yamamoto and
                  Masao Iriguchi and
                  Ewout Martens and
                  Jan Craninckx},
  title        = {A 60 dB {SNDR} 35 MS/s {SAR} {ADC} With Comparator-Noise-Based Stochastic
                  Residue Estimation},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {50},
  number       = {9},
  pages        = {2002--2011},
  year         = {2015},
  url          = {https://doi.org/10.1109/JSSC.2015.2422781},
  doi          = {10.1109/JSSC.2015.2422781},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/VerbruggenTYIMC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/MalkiVMWC15,
  author       = {Badr Malki and
                  Bob Verbruggen and
                  Ewout Martens and
                  Piet Wambacq and
                  Jan Craninckx},
  editor       = {Wolfgang Pribyl and
                  Franz Dielacher and
                  Gernot Hueber},
  title        = {A 150 kHz-80 MHz {BW} {DT} analog baseband for {SDR} {RX} using a
                  5\({}^{\mbox{th}}\)-order {IIR} LPF, active {FIR} and 10b 300 MS/s
                  {ADC} in 28nm {CMOS}},
  booktitle    = {{ESSCIRC} Conference 2015 - 41\({}^{\mbox{st}}\) European Solid-State
                  Circuits Conference, Graz, Austria, September 14-18, 2015},
  pages        = {80--83},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ESSCIRC.2015.7313833},
  doi          = {10.1109/ESSCIRC.2015.7313833},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/esscirc/MalkiVMWC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icicdt/SpagnoloVDW15,
  author       = {Annachiara Spagnolo and
                  Bob Verbruggen and
                  Stefano D'Amico and
                  Piet Wambacq},
  title        = {High-speed analog-to-digital converters in downscaled {CMOS}},
  booktitle    = {2015 International Conference on {IC} Design {\&} Technology,
                  {ICICDT} 2015, Leuven, Belgium, June 1-3, 2015},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ICICDT.2015.7165903},
  doi          = {10.1109/ICICDT.2015.7165903},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/icicdt/SpagnoloVDW15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/MalkiYVWC14,
  author       = {Badr Malki and
                  Takaya Yamamoto and
                  Bob Verbruggen and
                  Piet Wambacq and
                  Jan Craninckx},
  title        = {A 70 dB {DR} 10 b 0-to-80 MS/s Current-Integrating {SAR} {ADC} With
                  Adaptive Dynamic Range},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {49},
  number       = {5},
  pages        = {1173--1183},
  year         = {2014},
  url          = {https://doi.org/10.1109/JSSC.2014.2309086},
  doi          = {10.1109/JSSC.2014.2309086},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/MalkiYVWC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LiempdBMCSVC14,
  author       = {Barend van Liempd and
                  Jonathan Borremans and
                  Ewout Martens and
                  Sungwoo Cha and
                  Hans Suys and
                  Bob Verbruggen and
                  Jan Craninckx},
  title        = {A 0.9 {V} 0.4-6 GHz Harmonic Recombination {SDR} Receiver in 28 nm
                  {CMOS} With {HR3/HR5} and {IIP2} Calibration},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {49},
  number       = {8},
  pages        = {1815--1826},
  year         = {2014},
  url          = {https://doi.org/10.1109/JSSC.2014.2321148},
  doi          = {10.1109/JSSC.2014.2321148},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LiempdBMCSVC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/SpagnoloVWD14,
  author       = {Annachiara Spagnolo and
                  Bob Verbruggen and
                  Piet Wambacq and
                  Stefano D'Amico},
  title        = {A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved {ADC} in 40-nm {CMOS}},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {61-II},
  number       = {7},
  pages        = {466--470},
  year         = {2014},
  url          = {https://doi.org/10.1109/TCSII.2014.2327340},
  doi          = {10.1109/TCSII.2014.2327340},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/SpagnoloVWD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/SpagnoloVDW14,
  author       = {Annachiara Spagnolo and
                  Bob Verbruggen and
                  Stefano D'Amico and
                  Piet Wambacq},
  title        = {A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined {ADC} in 40nm
                  {CMOS}},
  booktitle    = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
                  Lido, Italy, September 22-26, 2014},
  pages        = {75--78},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ESSCIRC.2014.6942025},
  doi          = {10.1109/ESSCIRC.2014.6942025},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/esscirc/SpagnoloVDW14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/MalkiVWDIC14,
  author       = {Badr Malki and
                  Bob Verbruggen and
                  Piet Wambacq and
                  Kazuaki Deguchi and
                  Masao Iriguchi and
                  Jan Craninckx},
  title        = {A complementary dynamic residue amplifier for a 67 dB {SNDR} 1.36
                  mW 170 MS/s pipelined {SAR} {ADC}},
  booktitle    = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
                  Lido, Italy, September 22-26, 2014},
  pages        = {215--218},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ESSCIRC.2014.6942060},
  doi          = {10.1109/ESSCIRC.2014.6942060},
  timestamp    = {Fri, 02 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/esscirc/MalkiVWDIC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/VerbruggenDMC14,
  author       = {Bob Verbruggen and
                  Kazuaki Deguchi and
                  Badr Malki and
                  Jan Craninckx},
  title        = {A 70 dB {SNDR} 200 MS/s 2.3 mW dynamic pipelined {SAR} {ADC} in 28nm
                  digital {CMOS}},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858451},
  doi          = {10.1109/VLSIC.2014.6858451},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/VerbruggenDMC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/VerbruggenIC12,
  author       = {Bob Verbruggen and
                  Masao Iriguchi and
                  Jan Craninckx},
  title        = {A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined
                  {SAR} {ADC} in 40 nm Digital {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {12},
  pages        = {2880--2887},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2012.2217873},
  doi          = {10.1109/JSSC.2012.2217873},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/VerbruggenIC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/VerbruggenIC12,
  author       = {Bob Verbruggen and
                  Masao Iriguchi and
                  Jan Craninckx},
  title        = {A 1.7mW 11b 250MS/s 2{\texttimes} interleaved fully dynamic pipelined
                  {SAR} {ADC} in 40nm digital {CMOS}},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {466--468},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6177093},
  doi          = {10.1109/ISSCC.2012.6177093},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/VerbruggenIC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/MalkiYVWC12,
  author       = {Badr Malki and
                  Takaya Yamamoto and
                  Bob Verbruggen and
                  Piet Wambacq and
                  Jan Craninckx},
  title        = {A 70dB {DR} 10b 0-to-80MS/s current-integrating {SAR} {ADC} with adaptive
                  dynamic range},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {470--472},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6177095},
  doi          = {10.1109/ISSCC.2012.6177095},
  timestamp    = {Fri, 02 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/MalkiYVWC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/BorremansMGDISVC11,
  author       = {Jonathan Borremans and
                  Gunjan Mandal and
                  Vito Giannini and
                  Bj{\"{o}}rn Debaillie and
                  Mark Ingels and
                  Tomohiro Sano and
                  Bob Verbruggen and
                  Jan Craninckx},
  title        = {A 40 nm {CMOS} 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {7},
  pages        = {1659--1671},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2011.2144110},
  doi          = {10.1109/JSSC.2011.2144110},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/BorremansMGDISVC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/BorremansMGSIVC11,
  author       = {Jonathan Borremans and
                  Gunjan Mandal and
                  Vito Giannini and
                  Tomohiro Sano and
                  Mark Ingels and
                  Bob Verbruggen and
                  Jan Craninckx},
  title        = {A 40nm {CMOS} highly linear 0.4-to-6GHz receiver resilient to 0dBm
                  out-of-band blockers},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
                  Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
                  2011},
  pages        = {62--64},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISSCC.2011.5746220},
  doi          = {10.1109/ISSCC.2011.5746220},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/BorremansMGSIVC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/VerbruggenCKWP10,
  author       = {Bob Verbruggen and
                  Jan Craninckx and
                  Maarten Kuijk and
                  Piet Wambacq and
                  Geert Van der Plas},
  title        = {A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline {ADC} in 40 nm Digital
                  {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {10},
  pages        = {2080--2090},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2010.2061611},
  doi          = {10.1109/JSSC.2010.2061611},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/VerbruggenCKWP10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/VerbruggenCKWP10,
  author       = {Bob Verbruggen and
                  Jan Craninckx and
                  Maarten Kuijk and
                  Piet Wambacq and
                  Geert Van der Plas},
  title        = {A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined {ADC}
                  in 40nm digital {CMOS}},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {296--297},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433925},
  doi          = {10.1109/ISSCC.2010.5433925},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/VerbruggenCKWP10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/VerbruggenCKWP09,
  author       = {Bob Verbruggen and
                  Jan Craninckx and
                  Maarten Kuijk and
                  Piet Wambacq and
                  Geert Van der Plas},
  title        = {A 2.2 mW 1.75 GS/s 5 Bit Folding Flash {ADC} in 90 nm Digital {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {44},
  number       = {3},
  pages        = {874--882},
  year         = {2009},
  url          = {https://doi.org/10.1109/JSSC.2009.2012449},
  doi          = {10.1109/JSSC.2009.2012449},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/VerbruggenCKWP09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/RyckaertBVBACP09,
  author       = {Julien Ryckaert and
                  Jonathan Borremans and
                  Bob Verbruggen and
                  Lynn Bos and
                  Costantino Armiento and
                  Jan Craninckx and
                  Geert Van der Plas},
  title        = {A 2.4 GHz Low-Power Sixth-Order {RF} Bandpass {\(\Delta\)}{\(\Sigma\)}
                  Converter in {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {44},
  number       = {11},
  pages        = {2873--2880},
  year         = {2009},
  url          = {https://doi.org/10.1109/JSSC.2009.2028914},
  doi          = {10.1109/JSSC.2009.2028914},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/RyckaertBVBACP09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/PlasV08,
  author       = {Geert Van der Plas and
                  Bob Verbruggen},
  title        = {A 150 MS/s 133 {\(\mathrm{\mu}\)}W 7 bit {ADC} in 90 nm Digital {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {12},
  pages        = {2631--2640},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2008.2006315},
  doi          = {10.1109/JSSC.2008.2006315},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/PlasV08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/PlasV08,
  author       = {Geert Van der Plas and
                  Bob Verbruggen},
  title        = {A 150MS/s 133{\(\mu\)}W 7b {ADC} in 90nm digital {CMOS} Using a Comparator-Based
                  Asynchronous Binary-Search sub-ADC},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {242--243},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523147},
  doi          = {10.1109/ISSCC.2008.4523147},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/PlasV08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/VerbruggenCKWP08,
  author       = {Bob Verbruggen and
                  Jan Craninckx and
                  Maarten Kuijk and
                  Piet Wambacq and
                  Geert Van der Plas},
  title        = {A 2.2mW 5b 1.75GS/s Folding Flash {ADC} in 90nm Digital {CMOS}},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {252--253},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523152},
  doi          = {10.1109/ISSCC.2008.4523152},
  timestamp    = {Fri, 02 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/VerbruggenCKWP08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/WambacqMSVBHTLPPDDSCJ08,
  author       = {Piet Wambacq and
                  Abdelkarim Mercha and
                  Karen Scheir and
                  Bob Verbruggen and
                  Jonathan Borremans and
                  Vincent De Heyn and
                  Steven Thijs and
                  Dimitri Linten and
                  Geert Van der Plas and
                  Bertrand Parvais and
                  Morin Dehan and
                  Stefaan Decoutere and
                  Charlotte Soens and
                  Nadine Collaert and
                  Malgorzata Jurczak},
  title        = {Advanced Planar Bulk and Multigate {CMOS} Technology: Analog-Circuit
                  Benchmarking up to mm-Wave Frequencies},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {528--529},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523290},
  doi          = {10.1109/ISSCC.2008.4523290},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/WambacqMSVBHTLPPDDSCJ08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/WambacqVSBDLHPMPGSCJD07,
  author       = {Piet Wambacq and
                  Bob Verbruggen and
                  Karen Scheir and
                  Jonathan Borremans and
                  Morin Dehan and
                  Dimitri Linten and
                  Vincent De Heyn and
                  Geert Van der Plas and
                  Abdelkarim Mercha and
                  Bertrand Parvais and
                  Cedric Gustin and
                  Vaidyanathan Subramanian and
                  Nadine Collaert and
                  Malgorzata Jurczak and
                  Stefaan Decoutere},
  title        = {The Potential of FinFETs for Analog and {RF} Circuit Applications},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {54-I},
  number       = {11},
  pages        = {2541--2551},
  year         = {2007},
  url          = {https://doi.org/10.1109/TCSI.2007.907866},
  doi          = {10.1109/TCSI.2007.907866},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/WambacqVSBDLHPMPGSCJD07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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