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Hüseyin Dinc
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2020 – today
- 2020
- [j5]Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Matthew McShea, Joel Prabhakar, Scott Puckett:
A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration. IEEE J. Solid State Circuits 55(12): 3210-3224 (2020) - [c9]Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Mohit Kumar, Matthew McShea, Ryan Bunch, Joel Prabhakar, Scott Puckett:
16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration. ISSCC 2020: 250-252
2010 – 2019
- 2016
- [c8]Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Puckett, Andy Morgan, Ning Zhu, Qicheng Yu, Christopher Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, Scott Bardsley, Peter R. Derounian, Ryan Bunch, Ralph Moore, Gerry Taylor:
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither. VLSI Circuits 2016: 1-2 - 2014
- [j4]Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Russell Stop:
A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration. IEEE J. Solid State Circuits 49(12): 2857-2867 (2014) - [c7]Ahmed M. Abdelatty Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, David Jarman, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Ho-Young Lee:
29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration. ISSCC 2014: 482-483 - 2010
- [j3]Ahmed M. A. Ali, Andrew S. Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Paritosh Bhoraskar, Hüseyin Dinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed:
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration. IEEE J. Solid State Circuits 45(12): 2602-2612 (2010)
2000 – 2009
- 2009
- [j2]Hüseyin Dinc, Phillip E. Allen:
A 1.2 GSample/s Double-Switching CMOS THA With -62 dB THD. IEEE J. Solid State Circuits 44(3): 848-861 (2009) - 2006
- [c6]Erhan Ozalevli, Hüseyin Dinc, Haw-Jing Lo, Paul E. Hasler:
Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors. CICC 2006: 149-152 - 2005
- [c5]Hüseyin Dinc, Phillip E. Allen, Sudipto Chakraborty:
A low distortion, current feedback, programmable gain amplifier. ISCAS (5) 2005: 4819-4822 - [c4]Shengyuan Li, Hüseyin Dinc, Susanta Sengupta, Phillip E. Allen:
A high-speed wide-range low-distortion constant-gm cell design for GHz applications. ISCAS (5) 2005: 4823-4826 - [c3]Shengyuan Li, Susanta Sengupta, Huseyin Dinc, Phillip E. Allen:
CMOS high-linear wide-dynamic range RF on-chip filters using Q-enhanced LC filters. ISCAS (6) 2005: 5942-5945 - 2003
- [j1]Narayan Prasad Ramachandran, Hüseyin Dinç, Aydin I. Karsilayan:
A 3.3-V CMOS adaptive analog video line driver with low distortion performance. IEEE J. Solid State Circuits 38(6): 1051-1058 (2003) - 2002
- [c2]N. Prasad, Huseyin Dinc, Aydin I. Karsilayan:
An adaptive analog video line driver with impedance matching based on peak detection. ISCAS (4) 2002: 273-276 - 2001
- [c1]Ron Spencer, Huseyin Dinc, Taner Sumesaglam:
Associative amplitude modulation with built-in noise immunity. ICECS 2001: 631-636
Coauthor Index
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