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2000 – 2009
- 2002
[c6]Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian:
Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301- 2001
- [j1]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. 17(3-4): 283-290 (2001) - [c5]Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931 - 2000
- [c4]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328 - [c3]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Analyzing the test generation problem for an application-oriented test of FPGAs. ETW 2000: 75-80 - [c2]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI 2000: 3-8
1990 – 1999
- 1993
- [b1]Dennis de Champeaux, Doug Lea, Penelope Faure:
Object-oriented system development. Addison-Wesley 1993, ISBN 978-0-201-56355-9, pp. I-XVIII, 1-532 - 1992
- [c1]Dennis de Champeaux, Doug Lea, Penelope Faure:
The Process of Object-Oriented Design. OOPSLA 1992: 45-62
Coauthor Index
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