A Toolchain for Deterministic Parallelism on an Embedded Bare-metal Platform - Kenelm Louetsi; Christophe Nègre; David Parello (17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024, Kuala Lumpur, Malaysia, December 16-19, 2024, 2024)

Deterministic OpenMP and the LBP Parallelizing Manycore Processor - Bernard Goossens; Kenelm Louetsi; David Parello (Parallel Computing Technologies - 16th International Conference, PaCT 2021, Kaliningrad, Russia, September 13-18, 2021, Proceedings, 2021)

Optimizing Cherenkov Photons Generation and Propagation in CORSIKA for CTA Monte-Carlo Simulations - Luisa Arrabito; Konrad Bernlöhr; Johan Bregeon; Matthieu Carrère; Adnane Khattabi; Philippe Langlois; David Parello; Guillaume Revy (Comput. Softw. Big Sci., 2020)

Computing on many cores - Bernard Goossens; David Parello; Katarzyna Porada; Djallal Rahmoune (Concurr. Comput. Pract. Exp., 2017)

Reproducible, Accurately Rounded and Efficient BLAS - Chemseddine Chohra; Philippe Langlois; David Parello (Euro-Par 2016: Parallel Processing Workshops - Euro-Par 2016 International Workshops, Grenoble, France, August 24-26, 2016, Revised Selected Papers, 2016)

Parallel Locality and Parallelization Quality - Bernard Goossens; David Parello; Katarzyna Porada; Djallal Rahmoune (Proceedings of the 7th International Workshop on Programming Models and Applications for Multicores and Manycores, PMAM@PPoPP 2016, Barcelona, Spain, March 12-16, 2016, 2016)

Parallel Experiments with RARE-BLAS - Chemseddine Chohra; Philippe Langlois; David Parello (18th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, SYNASC 2016, Timisoara, Romania, September 24-27, 2016, 2016)

Toward a Core Design to Distribute an Execution on a Manycore Processor - Bernard Goossens; David Parello; Katarzyna Porada; Djallal Rahmoune (Parallel Computing Technologies - 13th International Conference, PaCT 2015, Petrozavodsk, Russia, August 31 - September 4, 2015, Proceedings, 2015)

Efficiency of Reproducible Level 1 BLAS - Chemseddine Chohra; Philippe Langlois; David Parello (Scientific Computing, Computer Arithmetic, and Validated Numerics - 16th International Symposium, SCAN 2014, Würzburg, Germany, September 21-26, 2014. Revised Selected Papers, 2014)

De quoi est faite une trace d'exécution ? - Bernard Goossens; Ali El Moussaoui; Ke Chen; David Parello (Tech. Sci. Informatiques, 2013)

Limits of Instruction-Level Parallelism Capture - Bernard Goossens; David Parello (Proceedings of the International Conference on Computational Science, ICCS 2013, Barcelona, Spain, 5-7 June, 2013, 2013)

Accélération de la simulation modulaire - Mourad Bouache; David Parello; Bernard Goossens (Tech. Sci. Informatiques, 2011)

Barra: A Parallel Functional Simulator for GPGPU - Caroline Collange; Marc Daumas; David Defour; David Parello (MASCOTS 2010, 18th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Miami, Florida, USA, August 17-19, 2010, 2010)

PerPI: A Tool to Measure Instruction Level Parallelism - Bernard Goossens; Philippe Langlois; David Parello; Eric Petit (Applied Parallel and Scientific Computing - 10th International Conference, PARA 2010, Reykjavík, Iceland, June 6-9, 2010, Revised Selected Papers, Part I, 2010)

Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies - Sylvain Girbal; Nicolas Vasilache; Cédric Bastoul; Albert Cohen; David Parello; Marc Sigler; Olivier Temam (Int. J. Parallel Program., 2006)

Facilitating the search for compositions of program transformations - Albert Cohen; Marc Sigler; Sylvain Girbal; Olivier Temam; David Parello; Nicolas Vasilache (Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, 2005)

Méthodologie d'optimisation de programmes pour architectures complexes de processeurs. (Program optimization methodology for complex processor architectures) - David Parello (University of Paris-Sud, Orsay, France, 2004)

Towards a Systematic, Pragmatic and Architecture-Aware Program Optimization Process for Complex Processors - David Parello; Olivier Temam; Albert Cohen; Jean-Marie Verdun (Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 6-12 November 2004, Pittsburgh, PA, USA, CD-Rom, 2004)

On increasing architecture awareness in program optimizations to bridge the gap between peak and sustained processor performance: matrix-multiply revisited - David Parello; Olivier Temam; Jean-Marie Verdun (Proceedings of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA, November 16-22, 2002, CD-ROM, 2002)