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ORCIDMuneo Fukaishi
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2010 – 2019
- 2012
[j14]Masaki Kitsunezuka, Hiroshi Kodama, Naoki Oshima, Kazuaki Kunihiro, Tadashi Maeda, Muneo Fukaishi:
A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems. IEEE J. Solid State Circuits 47(5): 1084-1093 (2012)- 2011
- [j13]Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi:
A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme. IEEE J. Solid State Circuits 46(3): 572-582 (2011) - [c8]Shingo Takahashi, Nobuhide Yoshida, Kenichi Maruhashi, Muneo Fukaishi:
Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems. ISSCC 2011: 220-222 - 2010
- [j12]Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau
, Nicolas Deparis, Nathalie Rolland, Muneo Fukaishi, Pierre Vincent:
A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI. IEEE J. Solid State Circuits 45(7): 1286-1294 (2010) - [j11]Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi:
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. IEEE J. Solid State Circuits 45(12): 2582-2590 (2010) - [c7]Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi:
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. ISSCC 2010: 470-471
2000 – 2009
- 2009
- [c6]Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau, Nicolas Deparis, Nathalie Rolland, Muneo Fukaishi, Pierre Vincent:
A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI. ESSCIRC 2009: 168-171 - 2007
- [j10]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits 42(1): 111-122 (2007) - [c5]Robert Payne, Muneo Fukaishi:
Multi-GB/s Transceivers. ISSCC 2007: 434-435 - 2006
- [j9]Kouichi Yamaguchi, Muneo Fukaishi:
Channel-Count-Independent BIST for Multi-Channel SerDes. IEICE Trans. Electron. 89-C(3): 314-319 (2006) - [c4]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC 2006: 1676-1685 - [c3]Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba:
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. ISSCC 2006: 1686-1695 - 2003
- [j8]Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno:
A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. IEEE J. Solid State Circuits 38(5): 741-746 (2003) - 2001
- [j7]Kouichi Yamaguchi, Muneo Fukaishi, Takehiko Sakamoto, Naoto Akiyama, Kazuyuki Nakamura:
A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture. IEEE J. Solid State Circuits 36(11): 1666-1672 (2001) - [c2]Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina:
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC 2001: 213-216 - [c1]Takashi Yoshikawa, Ichiro Hatakeyama, Kazunori Miyoshi, Kazuhiko Kurata, Juni-Ichi Sasaki, Nobuharu Kami, Takara Sugimoto, Muneo Fukaishi, Kazuyuki Nakamura, Kei Tanaka, Hiroaki Nishi, Tomohiro Kudoh:
Optical interconnection as an IP macro of a CMOS library. Hot Interconnects 2001: 31-35 - 2000
- [j6]Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi:
A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays. IEEE J. Solid State Circuits 35(11): 1611-1618 (2000)
1990 – 1999
- 1999
- [j5]Muneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuyanagi:
A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications. IEEE J. Solid State Circuits 34(9): 1325-1330 (1999) - 1998
- [j4]Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi:
A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture. IEEE J. Solid State Circuits 33(12): 2139-2147 (1998) - [j3]Masahiro Fujii, Keiichi Numata, Tadashi Maeda, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa:
A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 43-46 (1998) - 1996
- [j2]Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikam Hida, Yasuo Ohno:
A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's. IEEE J. Solid State Circuits 31(2): 240-246 (1996) - [j1]Tadashi Maeda, Keiichi Numata, Masahiro Fujii, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa:
An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF). IEEE J. Solid State Circuits 31(9): 1361-1363 (1996)
Coauthor Index
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