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Ho-Yong Choi

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2010 – 2019

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2014
[c5]
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Jung-Woong Park, Nam-Soo Kim, Hye-Im Jeong, Da-Sol Won, Ho-Yong Choi:
High performance two-stage charge-pump for spur reduction in CMOS PLL. SSD 2014: 1-7
[c4]
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Soo-Woo Kim, Se-Hyuk An, Nam-Soo Kim, Hye-Im Jeong, Ho-Yong Choi:
Circuit design for broad band EMI reduction in LCD driver IC. NORCHIP 2014: 1-4
2010
[c3]
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  - conf/iscas/ChoiS10
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Ho-Yong Choi, Kewal K. Saluja:
Detection of inter-port bridging faults in dual-port memories. ISCAS 2010: 657-660
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2000 – 2009

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2009
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Zhi-Yuan Cui, Yong-Gao Jin, Nam-Soo Kim, Ho-Yong Choi:
Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter. IEICE Trans. Electron. 92-C(8): 1073-1079 (2009)
2008
[j2]
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Do Danh Cuong, Zhi-Yuan Cui, Nam-Soo Kim, Kie-Yong Lee, Ho-Yong Choi:
Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter. IEICE Trans. Electron. 91-C(1): 81-86 (2008)
2007
[c2]
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  - conf/fgcn/JeonRCCK07
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Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang:
Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol. FGCN (2) 2007: 119-124
2002
[j1]
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Eunjung Oh, Soo-Hyun Kim, Dong-Ik Lee, Ho-Yong Choi:
High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2674-2683 (2002)
2001
[c1]
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Chan-Ho Park, Byung-Soo Choi, Dong-Ik Lee, Ho-Yong Choi:
Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure. ARVLSI 2001: 202-212
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