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ORCIDNobuki Kajihara
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2020 – today
- 2024
[c10]Shigeki Matsumoto, Yuki Ichikawa, Nobuki Kajihara, Hakaru Tamukoh:
FPGA Implementation for Large Scale Reservoir Computing based on Chaotic Boltzmann Machine. ISCAS 2024: 1-5
2000 – 2009
- 2001
- [c9]Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Arithmetic Operation Oriented Reconfigurable Chip: RHW. FPL 2001: 618-622 - [c8]Masaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi:
Implementation of a Gate-Level Evolvable Hardware Chip. ICES 2001: 38-49 - 2000
- [c7]Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. FCCM 2000: 281-282
1990 – 1999
- 1999
- [j5]Tetsuya Higuchi, Nobuki Kajihara:
Evolvable Hardware Chips for Industrial Applications. Commun. ACM 42(4): 60-66 (1999) - [j4]Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani
, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi:
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. IEEE Trans. Computers 48(6): 628-639 (1999) - [j3]Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu:
Real-world applications of analog and digital evolvable hardware . IEEE Trans. Evol. Comput. 3(3): 220-235 (1999) - [c6]Isamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi:
An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller. AAAI/IAAI 1999: 182-187 - [c5]Isamu Kajitani, Masahiro Murakawa, Nobuki Kajihara, Masaya Iwata, Hidenori Sakanashi, Tetsuya Higuchi:
Evolvable Hardware Chips for Neural Network Applications. ICANNGA 1999: 127-134 - 1998
- [c4]Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi:
Evolvable Hardware Chip for High Precision Printer Image Compression. AAAI/IAAI 1998: 486-491 - [c3]Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi:
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. ICES 1998: 1-12 - 1996
- [c2]Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara:
SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. FCCM 1996: 148-156 - [c1]Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara:
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. Parcella 1996: 128-136
1980 – 1989
- 1989
- [j2]Nobuhiko Koike, Toshiyuki Nakata, Nobuki Kajihara:
MAN-YO: Mixed level parallel logic simulation engine. Syst. Comput. Jpn. 20(10): 31-38 (1989) - 1988
- [j1]Nobuki Kajihara, Satoshi Matsushita, Toshiyuki Nakata, Nobuhiko Koike:
Parallel neural network simulation machine: Neuman. Neural Networks 1(Supplement-1): 544 (1988)
Coauthor Index
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