Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations - Nitish Kumar Srivastava; Hanchen Jin; Shaden Smith; Hongbo Rong; David H. Albonesi; Zhiru Zhang (IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020, 2020)

CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores - Neeraj Kulkarni; Gonzalo Gonzalez-Pumariega; Amulya Khurana; Christine A. Shoemaker; Christina Delimitrou; David H. Albonesi (53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, 2020)

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product - Nitish Kumar Srivastava; Hanchen Jin; Jie Liu; David H. Albonesi; Zhiru Zhang (53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, 2020)

CuttleSys: Data-Driven Resource Management forInteractive Applications on Reconfigurable Multicores - Neeraj Kulkarni; Gonzalo Gonzalez-Pumariega; Amulya Khurana; Christine A. Shoemaker; Christina Delimitrou; David H. Albonesi (CoRR, 2020)

T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations - Nitish Kumar Srivastava; Hongbo Rong; Prithayan Barua; Guanyu Feng; Huanqi Cao; Zhiru Zhang; David H. Albonesi; Vivek Sarkar; Wenguang Chen; Paul Petersen; Geoff Lowney; Adam Herr; et al. (27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019, San Diego, CA, USA, April 28 - May 1, 2019, 2019)

Dynamic GPGPU Power Management Using Adaptive Model Predictive Control - Abhinandan Majumdar; Leonardo Piga; Indrani Paul; Joseph L. Greathouse; Wei Huang; David H. Albonesi (2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017, 2017)

DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks - Tayyar Rzayev; Saber Moradi; David H. Albonesi; Rajit Manohar (2017 International Joint Conference on Neural Networks, IJCNN 2017, Anchorage, AK, USA, May 14-19, 2017, 2017)

Toolbox for exploration of energy-efficient event processors for human-computer interaction - Tayyar Rzayev; David H. Albonesi; François Guimbretière; Rajit Manohar; Jaeyeon Kihm (2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017, 2017)

2015 International Symposium on Computer Architecture Influential Paper Award - David H. Albonesi (IEEE Micro, 2016)

Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling - Abhinandan Majumdar; Zhiru Zhang; David H. Albonesi (7th ACM/IEEE International Conference on Cyber-Physical Systems, ICCPS 2016, Vienna, Austria, April 11-14, 2016, 2016)

Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015 - Deborah T. Marr; David H. Albonesi (ACM, 2015)

Energy-comfort optimization using discomfort history and probabilistic occupancy prediction - Abhinandan Majumdar; Jason L. Setter; Justin R. Dobbs; Brandon M. Hencey; David H. Albonesi (International Green Computing Conference, IGCC 2014, Dallas, TX, USA, November 3-5, 2014, 2014)

Flicker: a dynamically adaptive architecture for power limited multicore systems - Paula Petrica; Adam M. Izraelevitz; David H. Albonesi; Christine A. Shoemaker (The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013, 2013)

Energy-aware meeting scheduling algorithms for smart buildings - Abhinandan Majumdar; David H. Albonesi; Pradip Bose (BuildSys '12 Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Buildings, Toronto, Canada, November 6, 2012, 2012)

A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors - Mark J. Cianchetti; David H. Albonesi (ACM J. Emerg. Technol. Comput. Syst., 2011)

A phase adaptive cache hierarchy for SMT processors - Sonia López; Oscar Garnica; David H. Albonesi; Steven G. Dropsho; Juan Lanchares; José Ignacio Hidalgo (Microprocess. Microsystems, 2011)

ReMAP: A Reconfigurable Architecture for Chip Multiprocessors - Matthew A. Watkins; David H. Albonesi (IEEE Micro, 2011)

Future Directions in Computer Architecture Research - David H. Albonesi (IEEE Micro, 2010)

Moving Forward - David H. Albonesi (IEEE Micro, 2010)

Scalable thread scheduling and global power management for heterogeneous many-core architectures - Jonathan A. Winter; David H. Albonesi; Christine A. Shoemaker (19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, Vienna, Austria, September 11-15, 2010, 2010)

Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors - Matthew A. Watkins; David H. Albonesi (19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, Vienna, Austria, September 11-15, 2010, 2010)

Adaptive Cache Memories for SMT Processors - Sonia López; Oscar Garnica; David H. Albonesi; Steven G. Dropsho; Juan Lanchares; José Ignacio Hidalgo (13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France, 2010)

ReMAP: A Reconfigurable Heterogeneous Multicore Architecture - Matthew A. Watkins; David H. Albonesi (43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA, 2010)

From the Editor in Chief: Welcome A-Board - David H. Albonesi (IEEE Micro, 2009)

Phastlane: a rapid transit optical routing network - Mark J. Cianchetti; Joseph C. Kerekes; David H. Albonesi (36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, 2009)

42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA - David H. Albonesi; Margaret Martonosi; David I. August; José F. Martínez (ACM, 2009)

Changes Ahead - David H. Albonesi (IEEE Micro, 2008)

Addressing thermal nonuniformity in SMT workloads - Jonathan A. Winter; David H. Albonesi (ACM Trans. Archit. Code Optim., 2008)

Scheduling algorithms for unpredictably heterogeneous CMP architectures - Jonathan A. Winter; David H. Albonesi (The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008)

Shared reconfigurable architectures for CMPS - Matthew A. Watkins; Mark J. Cianchetti; David H. Albonesi (FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, 2008)

Predictions of CMOS compatible on-chip optical interconnect - Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas Nelson; David H. Albonesi; Philippe M. Fauchet; Eby G. Friedman (Integr., 2007)

Standing on Solid Ground - David H. Albonesi (IEEE Micro, 2007)

On-Chip Optical Technology in Future Bus-Based Multicore Designs - Nevin Kirman; Meyrem Kirman; Rajeev K. Dokania; José F. Martínez; Alyssa B. Apsel; Matthew A. Watkins; David H. Albonesi (IEEE Micro, 2007)

Editor in Chief's Message: Truly "hot" chips - Do we still care? - David H. Albonesi (IEEE Micro, 2007)

More Hot Stuff - David H. Albonesi (IEEE Micro, 2007)

Mixing It Up - David H. Albonesi (IEEE Micro, 2007)

Productive and Healthy Debate - David H. Albonesi (IEEE Micro, 2007)

Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors - Sonia López; Steven G. Dropsho; David H. Albonesi; Oscar Garnica; Juan Lanchares (16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, 2007)

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches - Sonia López; Steve Dropsho; David H. Albonesi; Oscar Garnica; Juan Lanchares (High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, 2007)

On-chip optical interconnect for reduced delay uncertainty - Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas Nelson; David H. Albonesi; Philippe M. Fauchet; Eby G. Friedman (2nd Internationa ICST Conference on Nano-Networks, Nano-Net 2007, Catania, Italy, September 24-26, 2007, 2007)

Compatible phase co-scheduling on a CMP of multi-threaded processors - Ali El-Moursy; Rajeev Garg; David H. Albonesi; Sandhya Dwarkadas (20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006)

Localized microarchitecture-level voltage management - Yongkang Zhu; David H. Albonesi (International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006)

Synergistic temperature and energy management in GALS processor architectures - Yongkang Zhu; David H. Albonesi (Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, 2006)

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors - Nevin Kirman; Meyrem Kirman; Rajeev K. Dokania; José F. Martínez; Alyssa B. Apsel; Matthew A. Watkins; David H. Albonesi (39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, 2006)

Power-Efficient Error Tolerance in Chip Multiprocessors - M. Wasiur Rashid; Edwin J. Tan; Michael C. Huang; David H. Albonesi (IEEE Micro, 2005)

Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance - M. Wasiur Rashid; Edwin J. Tan; Michael C. Huang; David H. Albonesi (14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA, 2005)

Electrical and optical on-chip interconnects in scaled microprocessors - Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas Nelson; Philippe M. Fauchet; Eby G. Friedman; David H. Albonesi (International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, 2005)

A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity - Yongkang Zhu; David H. Albonesi; Alper Buyuktosunoglu (IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings, 2005)

Partitioning Multi-Threaded Processors with a Large Number of Threads - Ali El-Moursy; Rajeev Garg; David H. Albonesi; Sandhya Dwarkadas (IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings, 2005)

Predictions of CMOS compatible on-chip optical interconnect - Guoqing Chen; Hui Chen; Mikhail Haurylau; Nicholas Nelson; Philippe M. Fauchet; Eby G. Friedman; David H. Albonesi (The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, 2005)

QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education - Gregory J. Briggs; Edwin J. Tan; Nicholas A. Nelson; David H. Albonesi (Proceedings of the 2005 workshop on Computer architecture education - held in conjunction with the 32nd International Symposium on Computer Architecture, WCAE@ISCA 2005, Madison, Wisconsin, USA, June 5, 2005, 2005)

An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications - Wanli Liu; David H. Albonesi; John Gostomski; Lloyd Palum; Dave Hinterberger; Rick Wanzenried; Mark Indovina (J. Circuits Syst. Comput., 2004)

Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences - David H. Albonesi (IEEE Micro, 2004)

The Energy Impact of Aggressive Loop Fusion - Yongkang Zhu; Grigorios Magklis; Michael L. Scott; Chen Ding; David H. Albonesi (13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, 2004)

Hiding Synchronization Delays in a GALS Processor Microarchitecture - Greg Semeraro; David H. Albonesi; Grigorios Magklis; Michael L. Scott; Steven G. Dropsho; Sandhya Dwarkadas (10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, 2004)

Dynamically Trading Frequency for Complexity in a GALS Microprocessor - Steven G. Dropsho; Greg Semeraro; David H. Albonesi; Grigorios Magklis; Michael L. Scott (37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, 2004)

Dynamically Tuning Processor Resources with Adaptive Processing - David H. Albonesi; Rajeev Balasubramonian; Steve Dropsho; Sandhya Dwarkadas; Eby G. Friedman; Michael C. Huang; Volkan Kursun; Grigorios Magklis; Michael L. Scott; Greg Semeraro; Pradip Bose; Alper Buyuktosunoglu; et al. (Computer, 2003)

Guest Editors' Introduction: Power and Complexity Aware Design - Pradip Bose; David H. Albonesi; Diana Marculescu (IEEE Micro, 2003)

Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor - Grigorios Magklis; Greg Semeraro; David H. Albonesi; Steve Dropsho; Sandhya Dwarkadas; Michael L. Scott (IEEE Micro, 2003)

A Dynamically Tunable Memory Hierarchy - Rajeev Balasubramonian; David H. Albonesi; Alper Buyuktosunoglu; Sandhya Dwarkadas (IEEE Trans. Computers, 2003)

Front-End Policies for Improved Issue Efficiency in SMT Processors - Ali El-Moursy; David H. Albonesi (Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, 2003)

Dynamic Data Dependence Tracking and its Application to Branch Prediction - Lei Chen; Steve Dropsho; David H. Albonesi (Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, 2003)

Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor - Grigorios Magklis; Michael L. Scott; Greg Semeraro; David H. Albonesi; Steve Dropsho (30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, 2003)

Energy Efficient Co-Adaptive Instruction Fetch and Issue - Alper Buyuktosunoglu; Tejas Karkhanis; David H. Albonesi; Pradip Bose (30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, 2003)

Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors - Rajeev Balasubramonian; Sandhya Dwarkadas; David H. Albonesi (30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, 2003)

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power - Steve Dropsho; Alper Buyuktosunoglu; Rajeev Balasubramonian; David H. Albonesi; Sandhya Dwarkadas; Greg Semeraro; Grigorios Magklis; Michael L. Scott (2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, 2002)

Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling - Greg Semeraro; Grigorios Magklis; Rajeev Balasubramonian; David H. Albonesi; Sandhya Dwarkadas; Michael L. Scott (Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, 2002)

Tradeoffs in power-efficient issue queue design - Alper Buyuktosunoglu; David H. Albonesi; Pradip Bose; Peter W. Cook; Stanley Schuster (Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, 2002)

A microarchitectural-level step-power analysis tool - Wael El-Essawy; David H. Albonesi; Balaram Sinharoy (Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, 2002)

Managing static leakage energy in microprocessor functional units - Steve Dropsho; Volkan Kursun; David H. Albonesi; Sandhya Dwarkadas; Eby G. Friedman (Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, 2002)

Dynamic frequency and voltage control for a multiple clock domain microarchitecture - Greg Semeraro; David H. Albonesi; Steve Dropsho; Grigorios Magklis; Sandhya Dwarkadas; Michael L. Scott (Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, 2002)

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor - Pradip Bose; David M. Brooks; Alper Buyuktosunoglu; Peter W. Cook; K. Das; Philip G. Emma; Michael Gschwind; Hans M. Jacobson; Tejas Karkhanis; Prabhakar Kudva; Stanley Schuster; James E. Smith; et al. (Power-Aware Computer Systems, Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers, 2002)

A circuit level implementation of an adaptive issue queue for power-aware microprocessors - Alper Buyuktosunoglu; David H. Albonesi; Stanley Schuster; David M. Brooks; Pradip Bose; Peter W. Cook (Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, 2001)

Low-Voltage 0, 25 \(μ\)m CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors - Brian W. Curran; Mary Gifaldi; Jason Martin; Alper Buyuktosunoglu; Martin Margala; David H. Albonesi (SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, 2001)

Dynamically allocating processor resources between nearby and distant ILP - Rajeev Balasubramonian; Sandhya Dwarkadas; David H. Albonesi (Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, 2001)

Reducing the complexity of the register file in dynamic superscalar processors - Rajeev Balasubramonian; Sandhya Dwarkadas; David H. Albonesi (Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, 2001)

Runtime Reconfiguration Techniques for Efficient General-Purpose Computation - Bingxiong Xu; David H. Albonesi (IEEE Des. Test Comput., 2000)

Selective Cache Ways: On-Demand Cache Resource Allocation - David H. Albonesi (J. Instr. Level Parallelism, 2000)

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures - Rajeev Balasubramonian; David H. Albonesi; Alper Buyuktosunoglu; Sandhya Dwarkadas (Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000, 2000)

An Adaptive Issue Queue for Reduced Power at High Performance - Alper Buyuktosunoglu; Stanley Schuster; David M. Brooks; Pradip Bose; Peter W. Cook; David H. Albonesi (Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, 2000)

STATS: A framework for microprocessor and system-level design space exploration - David H. Albonesi; Israel Koren (J. Syst. Archit., 1999)

An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures - David H. Albonesi (VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal, 1999)

Selective Cache Ways: On-Demand Cache Resource Allocation - David H. Albonesi (Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, 1999)

Dynamic IPC/Clock Rate Optimization - David H. Albonesi (Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, 1998)

Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems - David H. Albonesi; Israel Koren (Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, 1997)

A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques - David H. Albonesi; Israel Koren (Int. J. Parallel Program., 1996)

An analytical model of high performance superscalar-based multiprocessors - David H. Albonesi; Israel Koren (Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, PACT '95, Limassol, Cyprus, June 27-29, 1995, 1995)

Architecture and technology tradeoffs in the design of next-generation multiprocessor servers - David H. Albonesi; Israel Koren (Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, SPDP 1995, San Antonio, Texas , USA, October 25-28, 1995, 1995)

Tradeoffs in the Design of Single Chip Multiprocessors - David H. Albonesi; Israel Koren (Parallel Architectures and Compilation Techniques, Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT'94, Montréal, Canada, 24-26 August, 1994, 1994)