Spiridon F. Beldianu

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Sotirios G. Ziavras

> Home > Persons > Spiridon F. Beldianu

Publications

2015
[j4]
- view
  authority control:
- export record
  dblp key:
  - journals/tc/BeldianuZ15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tc/BeldianuZ15
Spiridon F. Beldianu, Sotirios G. Ziavras:
Performance-Energy Optimizations for Shared Vector Accelerators in Multicores. IEEE Trans. Computers 64(3): 805-817 (2015)
2014
[c5]
- view
  authority control:
- export record
  dblp key:
  - conf/sbac-pad/BeldianuZ14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/sbac-pad/BeldianuZ14
Spiridon F. Beldianu, Sotirios G. Ziavras:
ASIC Design of Shared Vector Accelerators for Multicore Processors. SBAC-PAD 2014: 182-189
2013
[j3]
- view
  authority control:
- export record
  dblp key:
  - journals/tecs/BeldianuZ13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tecs/BeldianuZ13
Spiridon F. Beldianu, Sotirios G. Ziavras:
Multicore-based vector coprocessor sharing for performance and energy gains. ACM Trans. Embed. Comput. Syst. 13(2): 17:1-17:25 (2013)
[c4]
- view
  authority control:
- export record
  dblp key:
  - conf/asap/SureshBZ13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asap/SureshBZ13
Shashank Suresh, Spiridon F. Beldianu, Sotirios G. Ziavras:
FPGA and ASIC square root designs for high performance and power efficiency. ASAP 2013: 269-272
[c3]
- view
  authority control:
- export record
  dblp key:
  - conf/issoc/BeldianuZ13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/issoc/BeldianuZ13
Spiridon F. Beldianu, Sotirios G. Ziavras:
Efficient on-chip vector processing for multicore processors. ISSoC 2013: 1-4
2012
[j2]
- view
  authority control:
- export record
  dblp key:
  - journals/mam/BeldianuDSZ12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mam/BeldianuDSZ12
Spiridon F. Beldianu, Christopher Dahlberg, Timothy Steele, Sotirios G. Ziavras:
Versatile design of shared vector coprocessors for multicores. Microprocess. Microsystems 36(7): 543-554 (2012)
2011
[c2]
- view
  authority control:
- export record
  dblp key:
  - conf/pdp/BeldianuZ11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/pdp/BeldianuZ11
Spiridon F. Beldianu, Sotirios G. Ziavras:
On-chip Vector Coprocessor Sharing for Multicores. PDP 2011: 431-438
2010
[j1]
- view
  authority control:
- export record
  dblp key:
  - journals/icl/BeldianuROZ10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/icl/BeldianuROZ10
Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras:
Scheduling for input-queued packet switches by a re-configurable parallel match evaluator. IEEE Commun. Lett. 14(4): 357-359 (2010)
2009
[c1]
- view
  authority control:
- export record
  dblp key:
  - conf/icccn/BeldianuROZ09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icccn/BeldianuROZ09
Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras:
Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches. ICCCN 2009: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.