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ORCIDSergey Y. Shumarayev
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2020 – today
- 2024
[j2]Wei Tang
, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits 59(4): 1235-1245 (2024)- [c15]Yuyang Wang, Songli Wang, Robert Parsons, Asher Novick, Vignesh Gopal, Kaylx Jang, Anthony Rizzo, Chia-Pin Chiu, Kaveh Hosseini, Tim Tri Hoang, Sergey Y. Shumarayev, Keren Bergman:
Silicon Photonics Chip I/O for Ultra High-Bandwidth and Energy-Efficient Die-to-Die Connectivity. CICC 2024: 1-8 - 2023
- [c14]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c13]Sergey Y. Shumarayev, Allen Chan, Tim Hoang, Robert Keller:
Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications. HCS 2022: 1-20 - [c12]Kaveh Hosseini, Edwin Kok, Sergey Y. Shumarayev, Daniel Jeong, Allen Chan, Austin Katzin, Songtao Liu, Radek Roucka, Manan Raval, Minh Mac, Chia-Pin Chiu, Thungoc Tran, Kumar Abhishek Singh, Sangeeta Raman, Yanjing Ke, Chen Li, Li-Fan Yang, Paulo Chao, Haiwei Lu, Fernando Luna, Xiaoqian Li, Tim Tri Hoang, Arnab Sarkar, Asako Toda, Ravi Mahajan, Nitin Deshpande, Conor O'Keeffe, Uma Krishnamoorthy, Vladimir Stojanovic, Christopher Madden, Chong Zhang, Matt Sysak, Pavan Bhargava, Chen Sun, Mark Wade:
5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O. VLSI Technology and Circuits 2022: 260-261 - 2021
- [c11]Kaveh Hosseini, Edwin Kok, Sergey Y. Shumarayev, Chia-Pin Chiu, Arnab Sarkar, Asako Toda, Yanjing Ke, Allen Chan, Daniel Jeong, Mason Zhang, Sangeeta Raman, Thungoc Tran, Kumar Abhishek Singh, Pavan Bhargava, Chong Zhang, Haiwei Lu, Ravi Mahajan, Xiaoqian Li, Nitin Deshpande, Conor O'Keeffe, Tim Tri Hoang, Uma Krishnamoorthy, Chen Sun, Roy Meade, Vladimir Stojanovic, Mark Wade:
8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO. OFC 2021: 1-3 - 2020
- [j1]Mark T. Wade, Roy Meade, Chandru Ramamurthy, Michael Rust, Forrest Sedgwick, Vladimir Stojanovic, Derek Van Orden, Chong Zhang, Chen Sun, Sergey Y. Shumarayev, Conor O'Keeffe, Erik Anderson, Tim T. Hoang, David Kehlet, Ravi V. Mahajan, Matthew T. Guzy, Allen Chan, Tina Tran, Shahab Ardalan, Pavan Bhargava, Sidney Buchbinder, Michael L. Davenport, John Michael Fini, Haiwei Lu, Chen Li:
TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O. IEEE Micro 40(2): 63-71 (2020)
2010 – 2019
- 2018
- [c10]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA 2018: 287 - [c9]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL 2018: 106-110 - 2015
- [c8]Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang:
Arria™ 10 device architecture. CICC 2015: 1-8 - 2013
- [c7]Kanupriya Bhardwaj, Sriram Narayan, Sergey Y. Shumarayev, Thomas H. Lee:
A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS. ISSCC 2013: 412-413 - 2012
- [c6]Weichi Ding, Mingde Pan, Wilson Wong, Daniel Chow, Mike Peng Li, Sergey Y. Shumarayev:
On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing. ITC 2012: 1-7 - 2010
- [c5]Dan Mansur, Sergey Y. Shumarayev:
Introducing 28-nm stratix VFPGAs: Built for bandwidth. Hot Chips Symposium 2010: 1-23
2000 – 2009
- 2009
- [c4]Mike P. Li, Sergey Y. Shumarayev:
Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation. CICC 2009: 105-112 - 2007
- [c3]Simar Maangat, Toan Nguyen, Wilson Wong, Sergey Y. Shumarayev, Tina Tran, Tim Hoang, Richard Cliff:
Receiver Offset Cancellation in 90-nm PLD Integrated SERDES. CICC 2007: 265-267 - 2005
- [c2]Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski:
A signal integrity-based link performance simulation platform. CICC 2005: 725-728 - 2002
- [c1]Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev:
Interconnect enhancements for a high-speed PLD architecture. FPGA 2002: 3-10
Coauthor Index
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