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ORCIDGhavam G. Shahidi
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2020 – today
- 2020
[j8]Phil Oldiges
, Reinaldo A. Vega, Henry K. Utomo, Nick A. Lanzillo, Thomas Wassick, Juntao Li, Junli Wang, Ghavam G. Shahidi:
Chip Power-Frequency Scaling in 10/7nm Node. IEEE Access 8: 154329-154337 (2020)- [i1]Rick Boivie, Charanjit S. Jutla, Daniel Friedman, Ghavam G. Shahidi:
EM-Side-Channel Resistant Symmetric-Key Authentication Mechanism for Small Devices. IACR Cryptol. ePrint Arch. 2020: 966 (2020)
2010 – 2019
- 2019
- [j7]Ghavam G. Shahidi:
Chip Power Scaling in Recent CMOS Technology Nodes. IEEE Access 7: 851-856 (2019) - [c6]Ghavam G. Shahidi:
Slow-Down in Power Scaling and the End of Moore's Law? VLSI-DAT 2019: 1 - 2013
- [c5]Ghavam G. Shahidi:
From 2D-planar to 3D-non-planar device architecture: A scalable path forward? CICC 2013: 1-8 - 2010
- [c4]Ali Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam G. Shahidi:
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. ISSCC 2010: 152-153
2000 – 2009
- 2007
- [c3]Ghavam G. Shahidi:
Evolution of CMOS Technology at 32 nm and Beyond. CICC 2007: 413-416 - 2006
- [j6]David J. Frank, Wilfried Haensch, Ghavam G. Shahidi, Omer H. Dokumaci:
Optimizing CMOS technology for maximum performance. IBM J. Res. Dev. 50(4-5): 419-432 (2006) - 2002
- [j5]Ghavam G. Shahidi:
SOI technology for the GHz era. IBM J. Res. Dev. 46(2-3): 121-132 (2002)
1990 – 1999
- 1999
- [c2]Ghavam G. Shahidi, Atul Ajmera, Fariborz Assaderaghi, Ronald J. Bolam, Harold Hovel, Effendi Leobandung, Werner Rausch, Devendra Sadana, Dominic Schepis, Lawrence F. Wagner, Larry Wissel, Kun Wu, Bijan Davai:
Device and circuit design issues in SOI technology. CICC 1999: 339-346 - 1997
- [j4]Jente B. Kuang, Somnuk Ratanaphanyarat, Mary Jo Saccamango, Louis L.-C. Hsu, Roy C. Flaker, Lawrence F. Wagner, Shao-Fu Sanford Chu, Ghavam G. Shahidi:
SRAM bitline circuits on PD SOI: advantages and concerns. IEEE J. Solid State Circuits 32(6): 837-844 (1997) - 1996
- [c1]Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Gerald P. Coleman, Denny D. Tang, Dominic Schepis, Ronald Schulz, Fariborz Assadaraghi:
250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies. ISLPED 1996: 89-92 - 1995
- [j3]Charles W. Koburger III, William F. Clark, James W. Adkisson, Eric Adler, Paul E. Bakeman, Albert S. Bergendahl, Alan B. Botula, W. Chang, Bijan Davari, John H. Givens, Howard H. Hansen, Steven J. Holmes, David V. Horak, Chung Hon Lam, Jerome B. Lasky, Stephen E. Luce, Randy W. Mann, Glen L. Miles, James S. Nakos, Edward J. Nowak, Ghavam G. Shahidi, Yuan Taur, Francis R. White, Matthew R. Wordeman:
A half-micron CMOS logic generation. IBM J. Res. Dev. 39(1-2): 215-228 (1995) - [j2]Ghavam G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, J. Y.-C. Sun, Michael R. Polcari, Bijan Davari:
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. IBM J. Res. Dev. 39(1-2): 229-244 (1995) - [j1]Bijan Davari, Robert H. Dennard, Ghavam G. Shahidi:
CMOS scaling for high performance and low power-the next ten years. Proc. IEEE 83(4): 595-606 (1995)
1980 – 1989
- 1989
- [b1]Ghavam G. Shahidi:
Non-stationary transport effects in deep sub-micron channel Si mosfets. Massachusetts Institute of Technology, USA, 1989
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