Nikil Mehta

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with André DeHon

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Publications

2015
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Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction. ACM Trans. Reconfigurable Technol. Syst. 7(4): 32:1-32:23 (2015)
2013
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Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction. FPGA 2013: 81-90
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André DeHon, Nikil Mehta:
Exploiting partially defective LUTs: Why you don't need perfect fabrication. FPT 2013: 12-19
2012
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Nikil Mehta, Raphael Rubin, André DeHon:
Limit study of energy & delay benefits of component-specific routing. FPGA 2012: 97-106
2011
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Michael DeLorimier, Nachiket Kapre, Nikil Mehta, André DeHon:
Spatial hardware implementation for sparse graph algorithms in GraphStep. ACM Trans. Auton. Adapt. Syst. 6(3): 17:1-17:20 (2011)
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Nikil Mehta, André DeHon:
Low-Power Techniques for FPGAs. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 337-363
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Nikil Mehta, André DeHon:
Variation and Aging Tolerance in FPGAs. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 365-380
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Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon:
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 381-432
2006
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Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomás E. Uribe, Thomas F. Knight Jr., André DeHon:
GraphStep: A System Architecture for Sparse-Graph Algorithms. FCCM 2006: 143-151
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Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon:
Packet Switched vs. Time Multiplexed FPGA Overlay Networks. FCCM 2006: 205-216

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