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ORCIDNihar R. Mahapatra
Person information
- affiliation: Michigan State University, East Lansing, MI, USA
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2020 – today
- 2024
[c60]Dena F. Mujtaba, Nihar R. Mahapatra, Megan Arney, J. Scott Yaruss, Hope Gerlach-Houck, Caryn Herring, Jia Bin:
Lost in Transcription: Identifying and Quantifying the Accuracy Biases of Automatic Speech Recognition Systems Against Disfluent Speech. NAACL-HLT 2024: 4795-4809- [i3]Dena F. Mujtaba, Nihar R. Mahapatra, Megan Arney, J. Scott Yaruss, Hope Gerlach-Houck, Caryn Herring, Jia Bin:
Lost in Transcription: Identifying and Quantifying the Accuracy Biases of Automatic Speech Recognition Systems Against Disfluent Speech. CoRR abs/2405.06150 (2024) - [i2]Dena F. Mujtaba, Nihar R. Mahapatra:
Fairness in AI-Driven Recruitment: Challenges, Metrics, Methods, and Future Directions. CoRR abs/2405.19699 (2024) - [i1]Dena F. Mujtaba, Nihar R. Mahapatra, Megan Arney, J. Scott Yaruss, Caryn Herring, Jia Bin:
Inclusive ASR for Disfluent Speech: Cascaded Large-Scale Self-Supervised Learning with Targeted Fine-Tuning and Data Augmentation. CoRR abs/2406.10177 (2024) - 2022
- [c59]Dena F. Mujtaba, Nihar R. Mahapatra:
Deep Learning for Spatiotemporal Modeling of Illegal, Unreported, and Unregulated Fishing Events. CSCI 2022: 423-425 - [c58]Dena F. Mujtaba, Nihar R. Mahapatra:
A Study of Feature Importance in Fish Species Prediction Neural Networks. CSCI 2022: 1547-1550 - [c57]Dena F. Mujtaba, Nihar R. Mahapatra:
Hierarchical Deep Learning Models for Identification of Fish Species. CSCI 2022: 1558-1562 - 2021
- [c56]Dena F. Mujtaba, Nihar R. Mahapatra:
Multi-Task Deep Neural Networks for Multimodal Personality Trait Prediction. CSCI 2021: 85-91 - [c55]Dena F. Mujtaba, Nihar R. Mahapatra:
Lateral Flow Test Interpretation with Residual Networks. CSCI 2021: 1283-1286 - [c54]Dena F. Mujtaba, Nihar R. Mahapatra:
Convolutional Neural Networks for Morphologically Similar Fish Species Identification. CSCI 2021: 1553-1559 - [c53]Dena F. Mujtaba, Nihar R. Mahapatra:
Fish Species Classification with Data Augmentation. CSCI 2021: 1588-1593 - [c52]Dena F. Mujtaba, Nihar R. Mahapatra:
Multi-objective optimization of item selection in computerized adaptive testing. GECCO 2021: 1018-1026
2010 – 2019
- 2019
- [c51]Dena F. Mujtaba, Nihar R. Mahapatra:
Modeling the Automation Level of Cyber-Physical Systems Designed for Food Preparation. ISED 2019: 1-5 - [c50]Xavier Williams, Nihar R. Mahapatra:
Analysis of Affordance Detection Methods for Real-World Robotic Manipulation. ISED 2019: 1-5 - [c49]Dena F. Mujtaba, Nihar R. Mahapatra:
Ethical Considerations in AI-Based Recruitment. ISTAS 2019: 1-7 - 2018
- [j16]Hossam M. Ashtawy
, Nihar R. Mahapatra:
Boosted neural networks scoring functions for accurate ligand docking and ranking. J. Bioinform. Comput. Biol. 16(2): 1850004:1-1850004:18 (2018) - [j15]Hossam M. Ashtawy, Nihar R. Mahapatra:
Task-Specific Scoring Functions for Predicting Ligand Binding Poses and Affinity and for Screening Enrichment. J. Chem. Inf. Model. 58(1): 119-133 (2018) - [j14]Hossam M. Ashtawy, Nihar R. Mahapatra:
Descriptor Data Bank (DDB): A Cloud Platform for Multiperspective Modeling of Protein-Ligand Interactions. J. Chem. Inf. Model. 58(1): 134-147 (2018) - 2015
- [j13]Hossam M. Ashtawy, Nihar R. Mahapatra:
BgN-Score and BsN-Score: Bagging and boosting based ensemble neural networks scoring functions for accurate binding affinity prediction of protein-ligand complexes. BMC Bioinform. 16(S-4): S8 (2015) - [j12]Hossam M. Ashtawy, Nihar R. Mahapatra:
Machine-learning scoring functions for identifying native poses of ligands docked to known and novel proteins. BMC Bioinform. 16(S-6): S3 (2015) - [j11]Hossam M. Ashtawy, Nihar R. Mahapatra:
A Comparative Assessment of Predictive Accuracies of Conventional and Machine Learning Scoring Functions for Protein-Ligand Binding Affinity Prediction. IEEE ACM Trans. Comput. Biol. Bioinform. 12(2): 335-347 (2015) - 2013
- [c48]Hossam M. Ashtawy, Nihar R. Mahapatra:
Molecular Docking for Drug Discovery: Machine-Learning Approaches for Native Pose Prediction of Protein-Ligand Complexes. CIBB 2013: 15-32 - [c47]Hossam M. Ashtawy, Nihar R. Mahapatra:
Does Accurate Scoring of Ligands against Protein Targets Mean Accurate Ranking? ISBRA 2013: 298-310 - 2012
- [j10]Hossam M. Ashtawy, Nihar R. Mahapatra:
A Comparative Assessment of Ranking Accuracies of Conventional and Machine-Learning-Based Scoring Functions for Protein-Ligand Binding Affinity Prediction. IEEE ACM Trans. Comput. Biol. Bioinform. 9(5): 1301-1313 (2012) - 2011
- [c46]Hossam M. Ashtawy, Nihar R. Mahapatra:
A Comparative Assessment of Conventional and Machine-Learning-Based Scoring Functions in Predicting Binding Affinities of Protein-Ligand Complexes. BIBM 2011: 627-630 - 2010
- [c45]Jiangjiang Liu, Jianyong Zhang, Nihar R. Mahapatra:
Interconnect system compression analysis for multi-core architectures. SoCC 2010: 317-320
2000 – 2009
- 2009
- [c44]Sandeep K. Namilikonda, Nihar R. Mahapatra:
An Instance-Based Learning Approach for Available-Memory Non-minimal Cost-Bounded Search. ICMLA 2009: 202-207 - [c43]Sandeep K. Namilikonda, Nihar R. Mahapatra:
Dynamic User-Driven Available-Memory Non-Minimal Cost-Bounded Search. IICAI 2009: 130-145 - [c42]Sharath Jayaprakash, Nihar R. Mahapatra:
Energy-Efficient Encoding for High-Performance Buses with Staggered Repeaters. ISVLSI 2009: 252-257 - 2008
- [c41]Sandeep K. Namilikonda, Nihar R. Mahapatra:
Enhancing Available-Memory Cost-Bounded Iterative-Deepening Search. IC-AI 2008: 175-181 - [c40]Krishnan Sundaresan, Nihar R. Mahapatra:
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. ISQED 2008: 118-122 - [c39]Sharath Jayaprakash, Nihar R. Mahapatra:
Energy-optimal signaling and ordering of bits for area-constrained interconnects. SoCC 2008: 9-12 - [c38]Kaushal R. Gandhi, Nihar R. Mahapatra:
Partitioned reuse cache for energy-efficient soft-error protection of functional units. SoCC 2008: 17-20 - [c37]Jiangjiang Liu, Nihar R. Mahapatra:
The role of interconnects in the performance scalability of multicore architectures. SoCC 2008: 21-24 - [c36]Srivathsan Krishnamohan, Nihar R. Mahapatra:
Slack redistribution in pipelined circuits for enhanced soft-error rate reduction. SoCC 2008: 159-162 - [c35]Kaushal R. Gandhi, Nihar R. Mahapatra:
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass. VLSI Design 2008: 45-51 - 2007
- [j9]Nihar R. Mahapatra, Shantanu Dutt:
An efficient delay-optimal distributed termination detection algorithm. J. Parallel Distributed Comput. 67(10): 1047-1066 (2007) - [c34]Krishnan Sundaresan, Nihar R. Mahapatra:
An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. DAC 2007: 515-520 - [c33]Sharath Jayaprakash, Nihar R. Mahapatra:
Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. VLSI Design 2007: 127-134 - 2006
- [c32]Krishnan Sundaresan, Nihar R. Mahapatra:
Value-based bit ordering for energy optimization of on-chip global signal buses. DATE 2006: 624-625 - [c31]Kaushal R. Gandhi, Nihar R. Mahapatra:
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. DATE 2006: 1001-1006 - [c30]Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. ACM Great Lakes Symposium on VLSI 2006: 111-114 - [c29]Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. ICCD 2006: 17-24 - 2005
- [j8]Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, Srinivas Dangeti, Balakrishna V. Venkatrao:
A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost. J. Instr. Level Parallelism 7 (2005) - [c28]Srivathsan Krishnamohan, Nihar R. Mahapatra:
Combining Error Masking and Error Detection Plus Recovery to Combat Soft Errors in Static CMOS Circuits. DSN 2005: 40-49 - [c27]Srivathsan Krishnamohan, Nihar R. Mahapatra:
Analysis and design of soft-error hardened latches. ACM Great Lakes Symposium on VLSI 2005: 328-331 - [c26]Srivathsan Krishnamohan, Nihar R. Mahapatra:
An analysis of the robustness of CMOS delay elements. ACM Great Lakes Symposium on VLSI 2005: 412-415 - [c25]Srivathsan Krishnamohan, Nihar R. Mahapatra:
Increasing the energy efficiency of pipelined circuits via slack redistribution. ACM Great Lakes Symposium on VLSI 2005: 436-441 - [c24]Krishnan Sundaresan, Nihar R. Mahapatra:
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. HPCA 2005: 51-60 - [c23]Kaushal R. Gandhi, Nihar R. Mahapatra:
Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units. VLSI Design 2005: 570-575 - [c22]Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Energy-Efficient Compressed Address Transmission. VLSI Design 2005: 592-597 - [c21]Krishnan Sundaresan, Nihar R. Mahapatra:
An Accurate Energy and Thermal Model for Global Signal Buses. VLSI Design 2005: 685-690 - 2004
- [j7]Nihar R. Mahapatra, Shantanu Dutt:
Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. Parallel Comput. 30(5-6): 867-881 (2004) - [c20]Srivathsan Krishnamohan, Nihar R. Mahapatra:
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits. ICCD 2004: 126-131 - [c19]Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. ICCD 2004: 458-463 - [c18]Srivathsan Krishnamohan, Nihar R. Mahapatra:
An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits. SoCC 2004: 227-230 - 2003
- [c17]Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan:
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. ICCD 2003: 234-239 - [c16]Kaushal R. Gandhi, Nihar R. Mahapatra:
A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. ICCD 2003: 426- - [c15]Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, Srinivas Dangeti, Balakrishna V. Venkatrao:
The potential of compression to improve memory system performance, power consumption, and cost. IPCCC 2003: 343-350 - [c14]Jiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan:
Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. ISVLSI 2003: 220-221 - [c13]Krishnan Sundaresan, Nihar R. Mahapatra:
Code Compression Techniques for Embedded Systems and Their Effectiveness. ISVLSI 2003: 262-263 - 2002
- [c12]Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan:
The performance advantage of applying compression to the memory system. MSP/ISMM 2002: 86-96 - 2001
- [j6]Nihar R. Mahapatra, Shantanu Dutt:
Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. J. Parallel Distributed Comput. 61(10): 1391-1411 (2001) - 2000
- [j5]Nihar R. Mahapatra, Shantanu Dutt:
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. Int. J. Found. Comput. Sci. 11(2): 231-246 (2000) - [c11]Nihar R. Mahapatra, Sriram V. Garimella, Alwin Takeen:
Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation. ISCAS 2000: 537-540
1990 – 1999
- 1999
- [j4]Nihar R. Mahapatra, Balakrishna V. Venkatrao:
The processor-memory bottleneck: problems and solutions. XRDS 5(3es): 2-es (1999) - [c10]Nihar R. Mahapatra, Shantanu Dutt:
Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. FTCS 1999: 122-129 - [c9]Nihar R. Mahapatra, Douglas E. Covelli, Yuval Beres:
A Quantitative Evaluation of Limited-Memory Branch-and-Bound Algorithms. IC-AI 1999: 84-90 - [c8]Nihar R. Mahapatra, Alwin Tareen:
The role of computer technology trends in computer architecture education. WCAE@HPCA 1999: 3 - 1998
- [c7]Nihar R. Mahapatra, Shantanu Dutt:
Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems. IPPS/SPDP 1998: 796-800 - 1997
- [j3]Shantanu Dutt, Nihar R. Mahapatra:
Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. IEEE Trans. Computers 46(9): 997-1015 (1997) - [j2]Nihar R. Mahapatra, Shantanu Dutt:
Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. IEEE Trans. Parallel Distributed Syst. 8(7): 738-756 (1997) - 1996
- [c6]Nihar R. Mahapatra, Shantanu Dutt:
Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. FTCS 1996: 272-281 - [c5]Nihar R. Mahapatra, Shantanu Dutt:
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. IPPS 1996: 881-885 - 1995
- [c4]Shantanu Dutt, Nihar R. Mahapatra:
Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. FTCS 1995: 320-329 - 1994
- [j1]Shantanu Dutt, Nihar R. Mahapatra:
Scalable Load Balancing Strategies for Parallel A* Algorithms. J. Parallel Distributed Comput. 22(3): 488-505 (1994) - [c3]Nihar R. Mahapatra, Shantanu Dutt:
New Anticipatory Load Balancing Strategies for Parallel A* Algorithms. Parallel Processing of Discrete Optimization Problems 1994: 197-232 - 1993
- [c2]Shantanu Dutt, Nihar R. Mahapatra:
Parallel A* Algorithms and Their Performance on Hypercube Multiprocessors. IPPS 1993: 797-803 - [c1]Nihar R. Mahapatra, Shantanu Dutt:
Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. SPDP 1993: 290-297
Coauthor Index
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