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Ajith Pasqual
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2020 – today
- 2022
- [j2]Thilina S. Ambagahawaththa, Dulika Nayanasiri, Ajith Pasqual:
A Four-Step Method to Synthesize a DC-DC Converter for Multi-Inductor Realizable Arbitrary Voltage Conversion Ratio. IEEE Trans. Ind. Electron. 69(6): 5594-5603 (2022) - 2021
- [i2]Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual:
Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. CoRR abs/2109.03040 (2021)
2010 – 2019
- 2019
- [c17]Nisal Ranasinghe, Ravindu Bangamuarachchi, Jayath Seneviratne, Achini Jayawardane, Ajith Pasqual, R. M. A. U. Senarath:
SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks. ASAP 2019: 235-238 - [c16]Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual:
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. FPGA 2019: 117 - [c15]Kamlakannan Kamalavasan, Ratnasegar Natheesan, Kathirgamaraja Pradeep, Sivakumaran Gowthaman, Sivakaneshan Aravinth, Ajith Pasqual:
FPGA IP for Real-time 4K HDR Image Decoding in VR Devices. LASCAS 2019: 101-104 - [i1]Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual:
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. CoRR abs/1910.13683 (2019) - 2018
- [c14]Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual:
Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. ASAP 2018: 1-7 - [c13]Dakila Serasinghe, Duvindu Piyasena, Ajith Pasqual:
A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform. DSD 2018: 472-478 - [c12]Kathirgamaraja Pradeep, Kamalakkannan Kamalavasan, Ratnasegar Natheesan, Ajith Pasqual:
EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA. ICECS 2018: 81-84 - 2017
- [c11]Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual:
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. ASAP 2017: 164-169 - [c10]P. M. K. Tharaka, D. M. D. Wijerathne, Navoda Perera, Dinushan Vishwajith, Ajith Pasqual:
Runtime rule-reconfigurable high throughput NIPS on FPGA. FPT 2017: 251-254 - [c9]Kosala Perera, Udesh Gunarathne, Binal Chathuranga, Chamika Ramanayake, Ajith Pasqual:
Hybrid Software Defined Networking Controller. DCNET 2017: 77-84 - [c8]Ayanga D. Kalupahana, Nisal Hemadasa, Nipun Wijerathne, Anuranga Ranasinghe, Ajith Pasqual:
FPAA and FPGA based universal sensor node design. ICST 2017: 1-6 - 2016
- [j1]Maleen Abeydeera, Manupa Karunaratne, Geethan Karunaratne, Kalana De Silva, Ajith Pasqual:
4K Real-Time HEVC Decoder on an FPGA. IEEE Trans. Circuits Syst. Video Technol. 26(1): 236-249 (2016) - [c7]Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera, Ajith Pasqual:
Real time all intra HEVC HD encoder on FPGA. ASAP 2016: 191-195 - [c6]Viduranga Bandara Wijekoon, T. M. Dananjaya, P. H. Kariyawasam, S. Iddamalgoda, Ajith Pasqual:
High performance flow matching architecture for OpenFlow data plane. NFV-SDN 2016: 186-191 - 2015
- [c5]Maleen Abeydeera, Ajith Pasqual:
HEVC inverse transform architecture utilizing coefficient sparsity. ICIP 2015: 4848-4852 - 2012
- [c4]Samoda Gamage, Ajith Pasqual:
High performance parallel packet Classification architecture with Popular Rule Caching. ICON 2012: 52-57
2000 – 2009
- 2008
- [c3]Ravina Panangalage, Ajith Pasqual:
Impact of ICT on learning and teaching. ISTAS 2008: 1-10
1990 – 1999
- 1999
- [c2]Ajith Pasqual, Hidenori Takeshima, Kiyoharu Aizawa:
Software Based Object Tracking with Visual Feature Integration. ICIP (2) 1999: 963-967 - 1998
- [c1]Ajith Pasqual, Kiyoharu Aizawa, Mitsutoshi Hatori:
Selection/Substitution of Visual Features for Object Tracking. MVA 1998: 443-446
Coauthor Index
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