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ORCIDChristodoulos Peltekis
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2020 – today
- 2025
[i11]Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors. CoRR abs/2501.10189 (2025)- 2024
- [j3]Dionysios Filippas
, Christodoulos Peltekis, Vasileios Titopoulos, Ioannis Kansizoglou, Georgios Ch. Sirakoulis, Antonios Gasteratos, Giorgos Dimitrakopoulos:
A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators. IEEE Access 12: 57194-57208 (2024) - [j2]Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity. IEEE Comput. Archit. Lett. 23(1): 17-20 (2024) - [c7]Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos:
Reusing Softmax Hardware Unit for GELU Computation in Transformers. AICAS 2024: 159-163 - [c6]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos:
Error Checking for Sparse Systolic Tensor Arrays. AICAS 2024: 552-556 - [c5]Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. DATE 2024: 1-6 - [i10]Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity. CoRR abs/2401.08179 (2024) - [i9]Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos:
Reusing Softmax Hardware Unit for GELU Computation in Transformers. CoRR abs/2402.10118 (2024) - [i8]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos:
Error Checking for Sparse Systolic Tensor Arrays. CoRR abs/2402.10850 (2024) - [i7]Kosmas Alexandridis, Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos:
Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines. CoRR abs/2408.11997 (2024) - [i6]Christodoulos Peltekis, Giorgos Dimitrakopoulos:
GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks. CoRR abs/2412.18534 (2024) - 2023
- [j1]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Exploiting data encoding and reordering for low-power streaming in systolic arrays. Microprocess. Microsystems 102: 104938 (2023) - [c4]Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines. AICAS 2023: 1-5 - [c3]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos:
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. DATE 2023: 1-6 - [c2]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. MOCAST 2023: 1-4 - [i5]Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines. CoRR abs/2304.01668 (2023) - [i4]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. CoRR abs/2304.12691 (2023) - [i3]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos A. Nicopoulos:
The Case for Asymmetric Systolic Array Floorplanning. CoRR abs/2309.02969 (2023) - [i2]Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. CoRR abs/2311.07241 (2023) - 2022
- [c1]Christodoulos Peltekis, Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks. ASAP 2022: 93-97 - [i1]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos:
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. CoRR abs/2211.12600 (2022)
Coauthor Index
aka: Chrysostomos A. Nicopoulos
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