A 29-mm2, 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump. - Miyawaki, Yoshikazu; Ishizaki, Osamu; Okihara, Yoshihiko; Inaba, Tsutomu; Nitta, Fumihiko; Mihara, Masaaki; Hayasaka, Takashi; Kobayashi, Kazuo; Omae, Tadashi; Kimura, Hiroshi; Shimizu, Satoshi; Makimoto, Hiromi; et al. (IEEE J. Solid State Circuits, 1999)

A charge recycle refresh for Gb-scale DRAM's in file applications. - Kawahara, Takayulu; Kawajiri, Yoshiki; Horiguchi, Masashi; Akiba, Takesada; Kitsukawa, Goro; Kure, Tokuo; Aoki, Masakazu (IEEE J. Solid State Circuits, 1994)

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. - Kawahara, Takayuki; Sakata, Takeshi; Itoh, Kiyoo; Kawajiri, Yoshiki; Akiba, Takesada; Kitsukawa, Goro; Aoki, Masakazu (IEEE J. Solid State Circuits, 1993)

256-Mb DRAM circuit technologies for file applications. - Kitsukawa, Goro; Horiguchi, Masashi; Kawajiri, Yoshiki; Kawahara, Takayuki; Akiba, Takesada; Kawase, Yasushi; Tachibana, Toshikazu; Sakai, Takeshi; Aoki, Masakazu; Shukuri, Syoji; Sagara, Kazuhiko; Nagai, Ryo; et al. (IEEE J. Solid State Circuits, 1993)

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). - Kawahara, Takayuki; Horiguchi, Masashi; Kawajiri, Yoshiki; Kitsukawa, Goro; Kure, Tokuo; Aoki, Masakazu (IEEE J. Solid State Circuits, 1993)

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. - Kawahara, Takayuki; Kawajiri, Yoshiki; Kitsukawa, Goro; Sagara, Kazuhiko; Kawamoto, Yoshifumi; Akiba, Takesada; Kato, Shisei; Kawase, Yasushi; Itoh, Kiyoo (IEEE J. Solid State Circuits, 1992)

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. - Kawahara, Takayuki; Kawajiri, Yoshiki; Kitsukawa, Goro; Nakagome, Yoshinobu; Sagara, Kazuhiko; Kawamoto, Yoshifumi; Akiba, Takesada; Kato, Shisei; Kawase, Yasushi; Itoh, Kiyoo (IEEE J. Solid State Circuits, 1991)

A 23-ns 1-Mb BiCMOS DRAM. - Kitsukawa, Goro; Yanagisawa, Kazumasa; Kobayashi, Yutaka; Kinoshita, Yoshitaka; Ohta, Tatsuyuki; Udagawa, Tetsu; Miwa, Hitoshi; Miyazawa, Hiroyuki; Kawajiri, Yoshiki; Ouchi, Yoshiaki; Tsukada, Hiromi; Matsumoto, Tetsuro; et al. (IEEE J. Solid State Circuits, 1990)

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. - Kitsukawa, Goro; Itoh, Kiyoo; Hori, Ryoichi; Kawajiri, Yoshiki; Watanabe, Takao; Kawahara, Takayuki; Matsumoto, Tetsuro; Kobayashi, Yutaka (IEEE J. Solid State Circuits, 1989)

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. - Watanabe, Takao; Kitsukawa, Goro; Kawajiri, Yoshiki; Itoh, Kiyoo; Hori, Ryoichi; Ouchi, Yoshiaki; Kawahara, Takayuki; Matsumoto, Tetsuro (IEEE J. Solid State Circuits, 1989)

Substrate current reduction techniques for BiCMOS DRAM. - Kawahara, Takayuki; Kitsukawa, Goro; Higuchi, Hisayuki; Kawajiri, Yoshiki; Watanabe, Takao; Itoh, Kiyoo; Hori, Ryoichi; Kobayashi, Yutaka; Matsumoto, Tetsuro (IEEE J. Solid State Circuits, 1989)