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ORCIDJia Hou
Publications
- 2025
[j61]Yishuo Meng, Junfeng Wu, Siwei Xiang, Jianfei Wang
, Jia Hou, Zhijie Lin, Chen Yang:
A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method. IEEE Trans. Circuits Syst. I Regul. Pap. 72(2): 816-829 (2025)- [j60]Jianfei Wang, Chen Yang, Yishuo Meng, Fahong Zhang, Jia Hou, Siwei Xiang, Yang Su:
A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 72(3): 1358-1371 (2025) - [j59]Yishuo Meng, Jianfei Wang, Siwei Xiang, Jia Hou, Zhijie Lin, Kuizhi Mei, Chen Yang:
Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 72(8): 3983-3996 (2025) - [j58]Jianfei Wang, Chen Yang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Leibo Liu:
A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. IEEE Trans. Circuits Syst. II Express Briefs 72(1): 243-247 (2025) - [j57]Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang:
An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 72(1): 248-252 (2025) - [j54]Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang:
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. IEEE Trans. Very Large Scale Integr. Syst. 33(5): 1457-1461 (2025) - [c52]Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang:
Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. ASP-DAC 2025: 1302-1307 - 2024
- [j48]Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su:
A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2344-2348 (2024) - [j47]Yishuo Meng, Siwei Xiang, Jianfei Wang, Jia Hou, Chen Yang:
ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3473-3477 (2024) - 2023
- [j44]Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang:
POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection. Inf. 14(11): 604 (2023)
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