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ORCIDJung Hwan Kim
- > Home > Persons > Jung Hwan Kim
Publications
- 2008
[c22]Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, Jung Hwan Kim:
The Segmental-Transmission-Line: Its Design and Prototype Evaluation. ICES 2008: 130-140- 2005
- [c21]Daekwan Seo, Moritoshi Yasunaga, Insook Kim, Byungwoon Ham, Jung Hwan Kim:
Finding transcriptional regulatory elements in Dictyostelium gene expression. Congress on Evolutionary Computation 2005: 1746-1752 - 2004
- [c19]Daekwan Seo, Moritoshi Yasunaga, Jung Hwan Kim:
A computational approach to detect regulatory elements in Dictyostelium discoideum. IEEE Congress on Evolutionary Computation 2004: 1647-1653 - 2003
- [c17]Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim:
The design of segmental-transmission-line for high-speed digital signals using genetic algorithms. IEEE Congress on Evolutionary Computation 2003: 1748-1755 - [c15]Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim:
Gene Finding Using Evolvable Reasoning Hardware. ICES 2003: 198-207 - 2001
- [j8]Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara:
Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. Genet. Program. Evolvable Mach. 2(3): 211-230 (2001) - [j7]Jung Hwan Kim, Shanuj V. Sarin, Moritoshi Yasunaga, Hyunseo Oh:
Robust noncoherent PN-code acquisition for CDMA communication systems. IEEE Trans. Veh. Technol. 50(1): 278-286 (2001) - 2000
- [c12]Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim:
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. DFT 2000: 69-77 - [c11]Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara:
Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. Evolvable Hardware 2000: 253-262 - [c10]Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara:
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. FPGA 2000: 116-125 - [c9]Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim:
Kernel Optimization in Pattern Recognition Using a Genetic Algorithm. GECCO 2000: 391 - [c7]Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim:
Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. ICES 2000: 264-273 - 1999
- [c6]Moritoshi Yasunaga, Kenichi Tominaga, Jung Hwan Kim:
Parallel self-organization map using multiple stimuli. IJCNN 1999: 1127-1130 - 1998
- [j5]Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim:
Fault-tolerant self-organizing map implemented by wafer-scale integration. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 257-265 (1998)
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