SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (IEEE J. Solid State Circuits, 2023)

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem - Lluc Alvarez; Abraham Ruiz; Arnau Bigas-Soldevilla; Pavel Kuroedov; Alberto González; Hamsika Mahale; Noe Bustamante; Albert Aguilera; Francesco Minervini; Javier Salamero; Oscar Palomar; Vassilis Papaefstathiou; et al. (Proceedings of the 20th ACM International Conference on Computing Frontiers, CF 2023, Bologna, Italy, May 9-11, 2023, 2023)

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors - Lilia Zaourar; Alice Chillet; Jean-Marc Philippe (26th Euromicro Conference on Digital System Design, DSD 2023, Golem, Albania, September 6-8, 2023, 2023)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (CoRR, 2023)

Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions - Nermine Ali; Jean-Marc Philippe; Benoît Tain; Philippe Coussy (J. Signal Process. Syst., 2022)

Analysis of on-chip communication properties in accelerator architectures for deep neural networks - Hana Krichene; Jean-Marc Philippe (NOCS '21: International Symposium on Networks-on-Chip, Virtual Event, October 14-15, 2021, 2021)

Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators - Nermine Ali; Jean-Marc Philippe; Benoît Tain; Philippe Coussy (IEEE Workshop on Signal Processing Systems, SiPS 2021, Coimbra, Portugal, October 19-21, 2021, 2021)

Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems - Nermine Ali; Jean-Marc Philippe; Benoît Tain; Thomas Peyret; Philippe Coussy (IEEE Workshop on Signal Processing Systems, SiPS 2020, Coimbra, Portugal, October 20-22, 2020, 2020)

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000 exttimes Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency - Ivan Miro Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Anthony Quelen; Emmanuel Pluchart; Jean-Philippe Noel; Reda Boumchedda; et al. (IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020, 2020)

Task management on fully heterogeneous micro-server system: Modeling and resolution strategies - Lilia Zaourar; Massinissa Ait Aba; David Briand; Jean-Marc Philippe (Concurr. Comput. Pract. Exp., 2018)

PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks - Alexandre Carbon; Jean-Marc Philippe; Olivier Bichler; Renaud Schmit; Benoît Tain; David Briand; Nicolas Ventroux; Michel Paindavoine; Olivier Brousse (2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, 2018)

M2DC - Modular Microserver DataCentre with heterogeneous hardware - Ariel Oleksiak; Michal Kierzynka; Wojciech Piatek; Giovanni Agosta; Alessandro Barenghi; Carlo Brandolese; William Fornaciari; Gerardo Pelosi; Mariano Cecowski; Robert Plestenjak; Justin Cinkelj; Mario Porrmann; et al. (Microprocess. Microsystems, 2017)

Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System - Lilia Zaourar; Massinissa Ait Aba; David Briand; Jean-Marc Philippe (2017 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2017, Orlando / Buena Vista, FL, USA, May 29 - June 2, 2017, 2017)

The M2DC Project: Modular Microserver DataCentre - Mariano Cecowski; Giovanni Agosta; Ariel Oleksiak; Michal Kierzynka; Micha vor dem Berge; Wolfgang Christmann; Stefan Krupop; Mario Porrmann; Jens Hagemeyer; René Griessl; Meysam Peykanu; Lennart Tigges; et al. (2016 Euromicro Conference on Digital System Design, DSD 2016, Limassol, Cyprus, August 31 - September 2, 2016, 2016)

Data centres for IoT applications: The M2DC approach (Invited paper) - Michal Kierzynka; Ariel Oleksiak; Giovanni Agosta; Carlo Brandolese; William Fornaciari; Gerardo Pelosi; Micha vor dem Berge; Wolfgang Christmann; Stefan Krupop; Mariano Cecowski; Robert Plestenjak; Justin Cinkelj; et al. (International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016, 2016)

Exploration and design of embedded systems including neural algorithms - Jean-Marc Philippe; Alexandre Carbon; Olivier Brousse; Michel Paindavoine (Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015)

NeuroDSP Accelerator for Face Detection Application - Michel Paindavoine; Olivier Boisard; Alexandre Carbon; Jean-Marc Philippe; Olivier Brousse (Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, 2015)

HARS: A hardware-assisted runtime software for embedded many-core architectures - Yves Lhuillier; Maroun Ojail; Alexandre Guerre; Jean-Marc Philippe; Karim Ben Chehida; Farhat Thabet; Caaliph Andriamisaina; Chafic Jaber; Raphaël David (ACM Trans. Embed. Comput. Syst., 2014)

Parallel Architecture Benchmarking: From Embedded Computing to HPC, a FiPS Project Perspective - Yves Lhuillier; Jean-Marc Philippe; Alexandre Guerre; Michal Kierzynka; Ariel Oleksiak (12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, Milano, Italy, August 26-28, 2014, 2014)

An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture - Farhat Thabet; Yves Lhuillier; Caaliph Andriamisaina; Jean-Marc Philippe; Raphaël David (Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013)

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect - Sébastien Pillement; Olivier Sentieys; Jean-Marc Philippe (Microelectron. J., 2010)

A Self-reconfigurable FPGA-Based Platform for Prototyping Future Pervasive Systems - Jean-Marc Philippe; Benoît Tain; Christian Gamrat (Evolvable Systems: From Biology to Hardware - 9th International Conference, ICES 2010, York, UK, September 6-8, 2010. Proceedings, 2010)

Self-Adaptive Networked Entities for Building Pervasive Computing Architectures - Martin Danek; Jean-Marc Philippe; Petr Honzík; Christian Gamrat; Roman Bartosinski (Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, 2008)

An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency - Chris R. Jesshope; Jean-Marc Philippe; Michiel W. van Tol (Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings, 2008)

On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project - Katarina Paulsson; Michael Hübner; Jürgen Becker; Jean-Marc Philippe; Christian Gamrat (FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, 2007)

An energy-efficient ternary interconnection link for asynchronous systems - Jean-Marc Philippe; E. Kinvi-Boh; Sébastien Pillement; Olivier Sentieys (International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006)

Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects - Jean-Marc Philippe; Sébastien Pillement; Olivier Sentieys (7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, 2006)

A low-power and high-speed quaternary interconnection link using efficient converters - Jean-Marc Philippe; Sébastien Pillement; Olivier Sentieys (International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, 2005)