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Lide Duan
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2020 – today
- 2022
- [c18]Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC 2022: 1-3 - 2020
- [j11]Samuel Irving, Bin Li, Shaoming Chen, Lu Peng, Weihua Zhang, Lide Duan:
Computer comparisons in the presence of performance variation. Frontiers Comput. Sci. 14(1): 21-41 (2020) - [j10]Hao Yan, Hebin R. Cherian, Ethan C. Ahn
, Xuehai Qian, Lide Duan
:
iCELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration. IEEE Trans. Parallel Distributed Syst. 31(2): 408-422 (2020) - [i1]Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan:
Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks. CoRR abs/2008.01219 (2020)
2010 – 2019
- 2019
- [j9]Armin Haj Aboutalebi
, Ethan C. Ahn
, Bo Mao
, Suzhen Wu, Lide Duan
:
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2229-2242 (2019) - [c17]Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan:
Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification. ASAP 2019: 136 - [c16]Hongyu Liu, Sam Silvestro, Xiaoyin Wang, Lide Duan, Tongping Liu:
CSOD: Context-Sensitive Overflow Detection. CGO 2019: 50-60 - [c15]Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan:
Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks. IGSC 2019: 1-8 - 2018
- [j8]Bo Mao
, Suzhen Wu, Lide Duan:
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 472-484 (2018) - [c14]Hao Yan, Hebin R. Cherian, Ethan C. Ahn
, Lide Duan:
CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration. ICS 2018: 149-159 - [c13]Hao Yan, Armin Haj Aboutalebi, Lide Duan:
Efficient Allocation and Heterogeneous Composition of NVM Crossbar Arrays for Deep Learning Acceleration. IPCCC 2018: 1-8 - [c12]Swanand Mhalagi, Lide Duan, Paul Rad:
Designing and evaluating hybrid storage for high performance cloud computing. SysCon 2018: 1-8 - 2017
- [j7]Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin, Eugene John
:
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance. ACM Trans. Embed. Comput. Syst. 16(5s): 132:1-132:20 (2017) - [c11]Hao Yan, Ethan C. Ahn
, Lide Duan:
Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress. CASES 2017: 20:1-20:2 - [c10]Armin Haj Aboutalebi, Lide Duan:
Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress. CASES 2017: 21:1-21:2 - [c9]Armin Haj Aboutalebi, Lide Duan:
RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance. ICCD 2017: 625-632 - 2016
- [c8]Lei Jiang, Wujie Wen, Danghui Wang, Lide Duan:
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read. ASP-DAC 2016: 31-36 - 2015
- [j6]Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan:
Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors. Microprocess. Microsystems 39(4-5): 271-285 (2015) - [c7]Lide Duan, Dongyuan Zhan, Justin Hohnerlein:
Optimizing Cloud Data Center Energy Efficiency via Dynamic Prediction of CPU Idle Intervals. CLOUD 2015: 985-988 - 2014
- [j5]Ying Zhang, Lide Duan, Bin Li, Lu Peng, Xin Fu
:
Design configuration selection for hard-error reliable processors via statistical rules. Microprocess. Microsystems 38(1): 22-30 (2014) - [j4]Lide Duan, Ying Zhang, Bin Li, Lu Peng:
Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules. IEEE Trans. Computers 63(9): 2201-2214 (2014) - [c6]Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan:
Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors. ISQED 2014: 660-666 - 2013
- [j3]Lide Duan, Lu Peng, Bin Li:
Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing. IEEE Trans. Dependable Secur. Comput. 10(2): 114-127 (2013) - 2012
- [c5]Ying Zhang, Lide Duan, Bin Li, Lu Peng:
Optimal microarchitectural design configuration selection for processor hard-error reliability. ISQED 2012: 91-96 - 2011
- [c4]Lide Duan, Lu Peng, Bin Li:
Two-level soft error vulnerability prediction on SMT/CMP architectures. IISWC 2011: 78 - [c3]Lide Duan, Ying Zhang, Bin Li, Lu Peng:
Universal rules guided design parameter selection for soft error resilient processors. ISPASS 2011: 247-256 - 2010
- [j2]Ying Zhang, Lu Peng, Wencheng Lu, Lide Duan, Suresh Rai:
Expediating IP lookups with reduced power via TBM and SST supernode caching. Comput. Commun. 33(3): 390-397 (2010) - [j1]Bin Li, Lide Duan, Lu Peng:
Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions. IEEE Trans. Computers 59(5): 593-607 (2010)
2000 – 2009
- 2009
- [c2]Lide Duan, Bin Li, Lu Peng:
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics. HPCA 2009: 129-140 - 2007
- [c1]Lu Peng, Wencheng Lu, Lide Duan:
Power Efficient IP Lookup with Supernode Caching. GLOBECOM 2007: 215-219
Coauthor Index
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