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Kazushige Ayukawa

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2000 – 2009

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2001
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Seiji Miura, Kazushige Ayukawa, Takao Watanabe:
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. ISLPED 2001: 358-363

1990 – 1999

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1998
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Kazushige Ayukawa, Takao Watanabe, Susumu Narita:
An access-sequence control scheme to enhance random-access performance of embedded DRAM's. IEEE J. Solid State Circuits 33(5): 800-806 (1998)
1997
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Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome:
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. IEEE J. Solid State Circuits 32(5): 635-641 (1997)

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