Operating Coupled VO₂-Based Oscillators for Solving Ising Models. - Avedillo, Maria J.; Través, Manuel Jiménez; Delacour, Corentin; Todri-Sanial, Aida; Linares-Barranco, Bernabé; Núñez, Juan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Effect of Device Mismatches in Differential Oscillatory Neural Networks. - Shamsi, Jafar; Avedillo, Maria José; Linares-Barranco, Bernabé; Serrano-Gotarredona, Teresa (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. - Núñez, Juan; Avedillo, Maria J.; Través, Manuel Jiménez (2023)

How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. - Todri-Sanial, Aida; Carapezzi, Stefania; Delacour, Corentin; Abernot, Madeleine; Gil, Thierry; Corti, Elisabetta; Karg, Siegfried F.; Núñez, Juan; Través, Manuel Jiménez; Avedillo, Maria J.; Linares-Barranco, Bernabé (IEEE Trans. Neural Networks Learn. Syst., 2022)

Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. - Través, Manuel Jiménez; Avedillo, Maria José; Núñez, Juan; Linares-Barranco, Bernabé (2022)

Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. - Núñez, Juan; Thomann, Simon; Amrouch, Hussam; Avedillo, Maria J. (2022)

Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4. - Abernot, Madeleine; Gil, Thierry; Kurylin, Evgenii; Hardelin, Tanguy; Magueresse, Alexandre; Gonos, Théophile; Través, Manuel Jiménez; Avedillo, Maria José; Todri-Sanial, Aida (2022)

Effect of Device Mismatches in Differential Oscillatory Neural Networks. - Shamsi, Jafar; Avedillo, Maria José; Linares-Barranco, Bernabé; Serrano-Gotarredona, Teresa (CoRR, 2022)

Insights Into the Dynamics of Coupled VO2 Oscillators for ONNs. - Núñez, Juan; Quintana, José M.; Avedillo, Maria José; Través, Manuel Jiménez; Todri-Sanial, Aida; Corti, Elisabetta; Karg, Siegfried F.; Linares-Barranco, Bernabé (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks. - Shamsi, Jafar; Avedillo, Maria José; Linares-Barranco, Bernabé; Serrano-Gotarredona, Teresa (2020)

An Approach to the Device-Circuit Co-Design of HyperFET Circuits. - Través, Manuel Jiménez; Núñez, Juan; Avedillo, Maria José (2020)

Power and Speed Evaluation of Hyper-FET Circuits. - Núñez, Juan; Avedillo, Maria J. (IEEE Access, 2019)

Impact of the RT-level architecture on the power performance of tunnel transistor circuits. - Avedillo, Maria J.; Núñez, Juan (Int. J. Circuit Theory Appl., 2018)

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. - Quintero, Hector J.; Través, Manuel Jiménez; Avedillo, Maria J.; Núñez, Juan (2018)

Exploring logic architectures suitable for TFETs devices. - Núñez, Juan; Avedillo, Maria J. (2017)

Impact of pipeline in the power performance of tunnel transistor circuits. - Avedillo, Maria J.; Núñez, Juan (2016)

Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (IEEE Trans. Very Large Scale Integr. Syst., 2014)

DOE based high-performance gate-level pipelines. - Núñez, Juan; Avedillo, Maria J.; Quintero, Hector J. (2014)

Novel pipeline architectures based on Negative Differential Resistance devices. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (Microelectron. J., 2013)

Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (2013)

Bifurcation diagrams in MOS-NDR frequency divider circuits. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (2012)

Compact and Power Efficient MOS-NDR Muller C-Elements. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (2012)

Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (2012)

Efficient realization of RTD-CMOS logic gates. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (2011)

Evaluation of RTD-CMOS Logic Gates. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (2010)

Single phase MOS-NDR mobile networks. - Núñez, Juan; Avedillo, Maria J.; Quintana, José M. (2010)

An improved RNS generator 2n +/- k based on threshold logic. - Pettenghi, Héctor; Chaves, Ricardo; Sousa, Leonel; Avedillo, Maria J. (2010)

Operation Limits for RTD-Based MOBILE Circuits. - Quintana, José M.; Avedillo, Maria J.; Núñez, Juan; Pettenghi, Héctor (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. - Núñez, Juan; Quintana, José M.; Avedillo, Maria J. (2009)

Using multi-threshold threshold gates in RTD-based logic design: A case study. - Pettenghi, Héctor; Avedillo, Maria J.; Quintana, José M. (Microelectron. J., 2008)

Analysis of the critical rise time in MOBILE-based circuits. - Quintana, José M.; Avedillo, Maria J. (2008)

Limits to a correct operation in RTD-based ternary inverters. - Núñez, Juan; Quintana, José M.; Avedillo, Maria J. (2008)

A novel contribution to the RTD-based threshold logic family. - Pettenghi, Héctor; Avedillo, Maria J.; Quintana, José M. (2008)

Correct operation in SMOBILE-based quasi-differential quantizers. - Núñez, Juan; Quintana, José M.; Avedillo, Maria J. (2007)

Operation limits in RTD-based ternary quantizers. - Núñez, Juan; Quintana, José M.; Avedillo, Maria J. (2007)

Non Return Mobile Logic Family. - Pettenghi, Héctor; Avedillo, Maria J.; Quintana, José M. (2007)

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. - Núñez, Juan; Quintana, José M.; Avedillo, Maria J. (2007)

A quasi-differential quantizer based on SMOBILE. - Núñez, Juan; Quintana, José M.; Avedillo, Maria J. (2007)

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. - Avedillo, Maria J.; Quintana, José M.; Roldán, Héctor Pettenghi (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Design Guides for a Correct DC Operation in RTD-based Threshold Gates. - Quintana, José M.; Avedillo, Maria J.; Núñez, Juan (2006)

Limits to a Correct Evaluation in RTD-based Ternary Inverters. - Núñez, Juan; Quintana, José M.; Avedillo, Maria José (2006)

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. - Bol, David; Legat, Jean-Didier; Quintana, José M.; Avedillo, Maria José (2006)

Self-latching operation limits for MOBILE circuits. - Quintana, José M.; Avedillo, Maria J.; Pettenghi, Héctor (2006)

Analysis of frequency divider RTD circuits. - Quintana, José M.; Avedillo, Maria J. (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Logic Models Supporting the Design of MOBILE-based RTD Circuits. - Avedillo, Maria J.; Quintana, José M.; Pettenghi, Héctor (2005)

Robust frequency divider based on resonant tunneling devices. - Avedillo, Maria J.; Quintana, José M.; Huertas, José L. (2005)

Pass-transistor based implementations of threshold logic gates for WOS filtering. - Avedillo, Maria J.; Quintana, José M.; Jiménez-Naharro, Raúl (Microelectron. J., 2004)

A Practical Parallel Architecture for Stacks Filters. - Avedillo, Maria J.; Quintana, José M.; Alami, Hamid El; Jiménez-Calderón, Antonio (J. VLSI Signal Process., 2004)

A Threshold Logic Synthesis Tool for RTD Circuits. - Avedillo, Maria J.; Quintana, José M. (2004)

RTD-based compact programmable gates. - Quintana, José M.; Avedillo, Maria J.; Pettenghi, Héctor (2004)

Programmable logic gate based on resonant tunnelling devices. - Quintana, José M.; Avedillo, Maria J.; Pettenghi, Héctor (2004)

VLSI implementations of threshold logic-a comprehensive survey. - Beiu, Valeriu; Quintana, José M.; Avedillo, Maria J. (IEEE Trans. Neural Networks, 2003)

Review of Capacitive Threshold Gate Implementations. - Beiu, Valeriu; Avedillo, Maria J.; Quintana, José M. (2003)

Review of Differential Threshold Gate Implementations. - Beiu, Valeriu; Quintana, José M.; Avedillo, Maria J. (2003)

COPAS: A New Algorithm for the Partial Input Encoding Problem. - Martínez, Manuel; Avedillo, Maria José; Quintana, José M.; Huertas, José Luis (VLSI Design, 2002)

An Encoding Technique for Low Power CMOS Implementations of Controllers. - Martínez, Manuel; Avedillo, Maria J.; Quintana, José M.; Süß, H.; Koegst, Manfred (2002)

Threshold-logic-based design of compressors. - Quintana, José M.; Avedillo, Maria J.; Rodríguez-Villegas, Esther; Rueda, Adoración (2002)

High-speed low-power logic gates using floating gates. - Rodríguez-Villegas, Esther; Quintana, José M.; Avedillo, Maria J.; Rueda, Adoración (2002)

Simplified Reed-Muller expressions for residue threshold functions. - Quintana, José M.; Avedillo, Maria J.; Huertas, José L. (2002)

Simple parallel weighted order statistic filter implementations. - Avedillo, Maria J.; Quintana, José M.; Rodríguez-Villegas, Esther (2002)

Efficient Realization of a Threshold Voter for Self-Purging Redundancy. - Quintana, José M.; Avedillo, Maria J.; Huertas, José Luis (J. Electron. Test., 2001)

Two-Criterial Constraint-Driven FSM State Encoding for Low Power. - Koegst, Manfred; Rülke, Steffen; Franke, Günter; Avedillo, Maria J. (2001)

Practical low-cost CPL implementations threshold logic functions. - Quintana, José M.; Avedillo, Maria J.; Jiménez, Raúl; Rodríguez-Villegas, Esther (2001)

Low-power logic styles for full-adder circuits. - Quintana, José M.; Avedillo, Maria J.; Jiménez, Raúl; Rodríguez-Villegas, Esther (2001)

Reed-Muller descriptions of symmetric functions. - Quintana, José M.; Avedillo, Maria J. (2001)

νMOS-based Sorter for Arithmetic Applications. - Rodríguez-Villegas, Esther; Avedillo, Maria J.; Quintana, José M.; Huertas, Gloria; Rueda, Adoración (VLSI Design, 2000)

Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy. - Quintana, José M.; Avedillo, Maria J.; Rodríguez-Villegas, Esther; Rueda, Adoración (2000)

An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. - Martínez, Manuel; Avedillo, Maria J.; Quintana, José M.; Huertas, José L. (1999)

vMOS-based sorters for multiplier implementations. - Rodríguez-Villegas, Esther; Avedillo, Maria J.; Quintana, José M.; Huertas, Gloria; Rueda, Adoración (1999)

A Dynamic Model for the State Assignment Problem. - Martínez, Manuel; Avedillo, Maria J.; Quintana, José M.; Huertas, José L. (1998)

Constrained state assignment of easily testable FSMs. - Avedillo, Maria J.; Quintana, José M.; Huertas, José Luis (J. Electron. Test., 1995)

Optimum PLA folding through boolean satisfiability. - Quintana, José M.; Avedillo, Maria J.; Parra, Maria P.; Huertas, José L. (1995)

Easily Testable PLA-based FSMS. - Avedillo, Maria J.; Quintana, José M.; Huertas, José L. (1993)

A new method for the state reduction of incompletely specified finite sequential machines. - Avedillo, Maria J.; Quintana, José M.; Huertas, José Luis (1990)