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ORCIDElham K. Moghaddam
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2020 – today
- 2021
[j6]Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati
, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 76-88 (2021)
2010 – 2019
- 2019
- [j5]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada:
Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1028-1041 (2019) - [c14]Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki:
Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC 2019: 1-10 - 2018
- [j4]Michael Chen, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Hardware Protection via Logic Locking Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3020-3030 (2018) - 2017
- [j3]Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada:
Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2949-2961 (2017) - 2016
- [j2]Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On New Test Points for Compact Cell-Aware Tests. IEEE Des. Test 33(6): 7-14 (2016) - [c13]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On Test Points Enhancing Hardware Security. ATS 2016: 61-66 - [c12]Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer:
Minimal area test points for deterministic patterns. ITC 2016: 1-7 - [c11]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Test point insertion in hybrid test compression/LBIST architectures. ITC 2016: 1-10 - 2015
- [j1]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1847-1859 (2015) - [c10]Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada:
Design for low test pattern counts. DAC 2015: 136:1-136:6 - [c9]Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Embedded deterministic test points for compact cell-aware tests. ITC 2015: 1-8 - 2014
- [c8]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric test compression with low toggling activity. ITC 2014: 1-7 - 2011
- [c7]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki:
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium 2011: 267-272 - [c6]Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer:
Power Aware Embedded Test. Asian Test Symposium 2011: 511-516 - [c5]Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy:
Low power compression utilizing clock-gating. ITC 2011: 1-8 - 2010
- [c4]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab:
Low capture power at-speed test in EDT environment. ITC 2010: 714-723 - [c3]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab:
At-speed scan test with low switching activity. VTS 2010: 177-182
2000 – 2009
- 2007
- [c2]Elham K. Moghaddam, Shaahin Hessabi:
An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits. ATS 2007: 73-78 - [c1]Elham K. Moghaddam, Shaahin Hessabi:
An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. DSD 2007: 619-625
Coauthor Index
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