Temperature- and Voltage-Aware Timing Analysis. - Lasbouygues, B.; Wilson, Robin; Azémard, Nadine; Maurine, Philippe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Temperature and voltage aware timing analysis: application to voltage drops. - Lasbouygues, B.; Wilson, Robin; Azémard, Nadine; Maurine, Philippe (2007)

Logical effort model extension to propagation delay representation. - Lasbouygues, B.; Engels, Sylvain; Wilson, Robin; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Timing analysis in presence of supply voltage and temperature variations. - Lasbouygues, B.; Wilson, Robin; Azémard, Nadine; Maurine, Philippe (2006)

Temperature Dependency in UDSM Process. - Lasbouygues, B.; Wilson, Robin; Azémard, Nadine; Maurine, Philippe (2005)

Temperature Dependence in Low Power CMOS UDSM Process. - Lasbouygues, B.; Wilson, Robin; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2004)

Physical Extension of the Logical Effort Model. - Lasbouygues, B.; Wilson, Robin; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2004)

Continuous representation of the performance of a CMOS library. - Lasbouygues, B.; Schindler, Joel; Engels, Sylvain; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2003)