Pain versus Gain in the Hardware Design of FPUs and Supercomputers - Roger A. Golliver; Silvia M. Müller; Stuart F. Oberman; Martin S. Schmookler; Debjit Das Sarma; Andrew Beaumont-Smith (17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, 2005)

A VLSI chip implementation of an A/D converter error table compensator - Andrew Beaumont-Smith; John Tsimbinos; Cheng-Chew Lim; W. Marwood (Comput. Stand. Interfaces, 2001)

Parallel Prefix Adder Design - Andrew Beaumont-Smith; Cheng-Chew Lim (15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, 2001)

Reduced Latency IEEE Floating-Point Standard Adder Architectures - Andrew Beaumont-Smith; Neil Burgess; S. Lefrere; Cheng-Chew Lim (14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, 1999)

An array processor architecture for support vector learning - K. To; Cheng-Chew Lim; Andrew Beaumont-Smith; Michael J. Liebelt; W. Marwood (Third International Conference on Knowledge-Based Intelligent Information Engineering Systems, KES 1999, Adelaide, South Australia, 31 August - 1 September 1999, Proceedings, 1999)

A GaAs 32-bit Adder - Andrew Beaumont-Smith; Neil Burgess (13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, 1997)

Biologically inspired obstacle avoidance - a technology independent paradigm - Derek Abbott; Andre Yakovleff; Alireza Moini; X. Thong Nguyen; Andrew J. Blanksby; Richard Beare; Andrew Beaumont-Smith; Gyudong Kim; Abdesselam Bouzerdoum; Robert E. Bogner; Kamran Eshraghian (Mobile Robots X, Philadephia, PA, USA, October 23, 1995, Proceedings, 1995)