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2020 – today
- 2025
[j1]Minjin Tang
, Mei Wen, Jianchao Yang, Zeyu Xue, Junzhong Shen:
SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(2): 497-511 (2025)- 2024
- [c10]Minjin Tang, Mei Wen, Junzhong Shen, Jingkui Yang, Zeyu Xue, Zili Shao:
MSA2: An Efficient Sparsity-Aware Accelerator for Matrix Multiplication with Multi-core Systolic Arrays. ICA3PP (3) 2024: 263-282 - 2023
- [c9]Zeyu Xue, Mei Wen, Zhaoyun Chen, Yang Shi, Minjin Tang, Jianchao Yang, Zhongdi Luo:
Releasing the Potential of Tensor Core for Unstructured SpMM using Tiled-CSR Format. ICCD 2023: 457-464 - 2022
- [c8]Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei:
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys 2022: 126-134 - [c7]Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang:
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. ICCD 2022: 415-418 - [c6]Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu:
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP 2022: 18:1-18:11 - [i1]Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang:
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. CoRR abs/2209.09434 (2022) - 2021
- [c5]Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang:
SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. HPCC/DSS/SmartCity/DependSys 2021: 1049-1058 - 2020
- [c4]Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang:
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. DAC 2020: 1-6 - [c3]Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang:
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. FPGA 2020: 315 - [c2]Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang:
Optimized HybridSketch: More Efficient with Analysis and Algorithm. ICA3PP (1) 2020: 614-626 - [c1]Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang:
HybridSketch: A Memory-centric Precise Approach for Flow Measurement. ICC 2020: 1-7
Coauthor Index
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