A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur - Feng Bu; Ruixue Ding; Depeng Sun; Yuan Gao; Ruiqing Wang; Xiaoteng Zhao; Rong Zhou; Shubin Liu (Microelectron. J., 2025)

Design and analysis of an ultra-wideband quad-mode quad-core oscillator with mode ambiguity elimination - Ge Wang; Ruixue Ding; Dingtao Zeng; Feng Bu; Yuan Gao; Depeng Sun; Shubin Liu (Microelectron. J., 2025)

A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration - Feng Bu; Ruixue Ding; Depeng Sun; Ge Wang; Yuan Gao; Rong Zhou; Xiaoteng Zhao; Lisheng Chen; Shubin Liu; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

19.11 A 13GHz Charge-Pump PLL Achieving 15.8fs\(_rms\) Integrated Jitter and -98.5dBc Reference Spur - Depeng Sun; Feng Bu; Qixian Ye; Shijie Li; Yuan Gao; Bowen Wang; Hao Xu; Na Yan; Shubin Liu; Zhangming Zhu (IEEE International Solid-State Circuits Conference, ISSCC 2025, San Francisco, CA, USA, February 16-20, 2025, 2025)

A 39 GHz Doherty-Like Power Amplifier With 22dBm Output Power and 21% Power-Added Efficiency at 6dB Power Back-Off - Lang Chen; Lisheng Chen; Depeng Sun; Yichuang Sun; Yulin Pan; Xi Zhu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

A wideband low power RF Receiver Front-End for Internet-of-Things applications - Rong Zhou; Jianhang Yang; Linwei Wang; Xiaoteng Zhao; Shubin Liu; Depeng Sun (Microelectron. J., 2024)

A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators - Depeng Sun; Ruiqing Wang; Feng Bu; Yuan Gao; Xiaoteng Zhao; Ruixue Ding; Shubin Liu; Rong Zhou (Microelectron. J., 2024)

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs\(_rms\) Integrated Jitter and -250.8-dB FOM\(_PLL\) - Depeng Sun; Linguo Huang; Rong Zhou; Feng Bu; Lisheng Chen; Xiaoteng Zhao; Ruixue Ding; Shubin Liu; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.0006-mm\(^2\) 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS - Zhicheng Dong; Xiaoteng Zhao; Zekai Yang; Xianting Su; Haolin Han; Feng Bu; Rong Zhou; Depeng Sun; Yong Chen; Shubin Liu; Ruixue Ding; Zhangming Zhu (IEEE Asian Solid-State Circuits Conference, A-SSCC 2024, Hiroshima, Japan, November 18-21, 2024, 2024)

A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm\(^2\) Area - Zhicheng Dong; Xiaoteng Zhao; Weitan Huang; Yuan Gao; Depeng Sun; Shubin Liu; Lihong Yang; Zhangming Zhu (IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024, 2024)

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs - Depeng Sun; Ruixue Ding; Feng Bu; Hongzhi Liang; Dengquan Li; Yuhua Liang; Shubin Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 7b 400 8203MS/s pipelined SAR ADC in 65 8203nm CMOS - Ruixue Ding; Li Dang; Hanchao Lin; Depeng Sun; Shubin Liu; Zhangming Zhu (Microelectron. J., 2020)