A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Vivet, Pascal; Thonnart, Yvain; Lemaire, Romain; Santos, Cristiano; Beigné, Edith; Bernard, Christian; Darve, Florian; Lattard, Didier; Panades, Ivan Miro; Dutoit, Denis; Clermidy, Fabien; Cheramy, Séverine; et al. (IEEE J. Solid State Circuits, 2017)

IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system. - Durupt, Jean; Vivet, Pascal; Schloeffel, Juergen (2016)

3D DFT Challenges and Solutions. - Fkih, Yassine; Vivet, Pascal; Flottes, Marie-Lise; Rouzeyre, Bruno; Natale, Giorgio Di; Schloeffel, Juergen (2015)

Cell-Aware Test. - Hapke, Friedrich; Redemund, Wilfried; Glowatz, Andreas; Rajski, Janusz; Reese, Michael; Hustava, Marek; Keim, Martin; Schloeffel, Juergen; Fast, Anja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Cell-aware experiences in a high-quality automotive test suite. - Hapke, Friedrich; Arnold, Ralf; Beck, Matthias; Baby, M.; Straehle, S.; Goncalves, J. F.; Panait, A.; Behr, R.; Maugard, Gwenolé; Prashanthi, A.; Schloeffel, Juergen; Redemund, Wilfried; et al. (2014)

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. - Fkih, Yassine; Vivet, Pascal; Rouzeyre, Bruno; Flottes, Marie-Lise; Natale, Giorgio Di; Schloeffel, Juergen (2014)

Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates. - Hapke, Friedrich; Schlöffel, Jürgen (2012)

Cell-aware Production test results from a 32-nm notebook processor. - Hapke, Friedrich; Reese, Michael; Rivers, Jason; Over, A.; Ravikumar, V.; Redemund, Wilfried; Glowatz, Andreas; Schlöffel, Jürgen; Rajski, Janusz (2012)

Cell-aware analysis for small-delay effects and production test results from different fault models. - Hapke, Friedrich; Schlöffel, Jürgen; Redemund, Wilfried; Glowatz, Andreas; Rajski, Janusz; Reese, Michael; Rearick, J.; Rivers, Jason (2011)

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. - Eggersglüß, Stephan; Fey, Görschwin; Glowatz, Andreas; Hapke, Friedrich; Schlöffel, Jürgen; Drechsler, Rolf (J. Electron. Test., 2010)

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. - Tille, Daniel; Eggersglüß, Stephan; Krenz-Baath, Rene; Schlöffel, Jürgen; Drechsler, Rolf (2010)

Defect-oriented cell-internal testing. - Hapke, Friedrich; Redemund, Wilfried; Schlöffel, Jürgen; Krenz-Baath, Rene; Glowatz, Andreas; Wittke, Michael; Hashempour, Hamidreza; Eichenberger, Stefan (2010)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). - Drechsler, Rolf; Eggersglüß, Stephan; Fey, Görschwin; Schlöffel, Jürgen; Tille, Daniel (it Inf. Technol., 2009)

SUPERB: Simulator utilizing parallel evaluation of resistive bridges. - Engelke, Piet; Becker, Bernd; Renovell, Michel; Schlöffel, Jürgen; Braitling, Bettina; Polian, Ilia (ACM Trans. Design Autom. Electr. Syst., 2009)

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. - Hapke, Friedrich; Krenz-Baath, Rene; Glowatz, Andreas; Schlöffel, Jürgen; Hashempour, Hamidreza; Eichenberger, Stefan; Hora, Camelia; Adolfsson, Dan (2009)

Restrict Encoding for Mixed-Mode BIST. - Hakmi, Abdul Wahid; Holst, Stefan; Wunderlich, Hans-Joachim; Schlöffel, Jürgen; Hapke, Friedrich; Glowatz, Andreas (2009)

On Acceleration of SAT-Based ATPG for Industrial Designs. - Drechsler, Rolf; Eggersglüß, Stephan; Fey, Görschwin; Glowatz, Andreas; Hapke, Friedrich; Schlöffel, Jürgen; Tille, Daniel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Resistive Bridging Fault Simulation of Industrial Circuits. - Engelke, Piet; Polian, Ilia; Schlöffel, Jürgen; Becker, Bernd (2008)

Deterministic logic BIST for transition fault testing. - Gherman, Valentin; Wunderlich, Hans-Joachim; Schlöffel, Jürgen; Garbers, Michael (IET Comput. Digit. Tech., 2007)

Computation and Application of Absolute Dominators in Industrial Designs. - Krenz-Baath, Rene; Glowatz, Andreas; Schlöffel, Jürgen (2007)

Synthesis of irregular combinational functions with large don't care sets. - Gherman, Valentin; Wunderlich, Hans-Joachim; Mascarenhas, R. D.; Schlöffel, Jürgen; Garbers, Michael (2007)

Experimental Studies on SAT-Based ATPG for Gate Delay Faults. - Eggersglüß, Stephan; Tille, Daniel; Fey, Görschwin; Drechsler, Rolf; Glowatz, Andreas; Hapke, Friedrich; Schlöffel, Jürgen (2007)

Programmable deterministic Built-In Self-Test. - Hakmi, Abdul Wahid; Wunderlich, Hans-Joachim; Zoellin, Christian G.; Glowatz, Andreas; Hapke, Friedrich; Schlöffel, Jürgen; Souef, Laurent (2007)

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. - Eggersglüß, Stephan; Fey, Görschwin; Drechsler, Rolf; Glowatz, Andreas; Hapke, Friedrich; Schlöffel, Jürgen (2007)

X-masking during logic BIST and its impact on defect coverage. - Tang, Yuyi; Wunderlich, Hans-Joachim; Engelke, Piet; Polian, Ilia; Becker, Bernd; Schlöffel, Jürgen; Hapke, Friedrich; Wittke, Michael (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Fault detection and diagnosis with parity trees for space compaction of test responses. - Vranken, Harald P. E.; Goel, Sandeep Kumar; Glowatz, Andreas; Schlöffel, Jürgen; Hapke, Friedrich (2006)

Deterministic Logic BIST for Transition Fault Testing. - Gherman, Valentin; Wunderlich, Hans-Joachim; Schlöffel, Jürgen; Garbers, Michael (2006)

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. - Palit, Ajoy Kumar; Wu, Lei; Duganapalli, Kishore K.; Anheier, Walter; Schlöffel, Jürgen (2005)

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. - Shi, Junhao; Fey, Görschwin; Drechsler, Rolf; Glowatz, Andreas; Hapke, Friedrich; Schlöffel, Jürgen (2005)

ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. - Palit, Ajoy Kumar; Meyer, Volker; Anheier, Walter; Schlöffel, Jürgen (2005)

Implementing a Scheme for External Deterministic Self-Test. - Hakmi, Abdul Wahid; Wunderlich, Hans-Joachim; Gherman, Valentin; Garbers, Michael; Schlöffel, Jürgen (2005)

Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. - Palit, Ajoy Kumar; Meyer, Volker; Anheier, Walter; Schlöffel, Jürgen (2004)

PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. - Herrmann, Andreas; Barke, Erich; Silvant, Mathias; Schlöffel, Jürgen (2000)