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ORCIDRezgar Sadeghi
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2020 – today
- 2022
[c7]Rezgar Sadeghi, Ehsan Akbari, Mohamad Ali Saber:
On-Chip Training of Crosstalk Predictors to Fit Uncertainties. ETS 2022: 1-2- 2020
- [j1]Mohammad Ebrahimi
, Rezgar Sadeghi, Zainalabedin Navabi:
LUT Input Reordering to Reduce Aging Impact on FPGA LUTs. IEEE Trans. Computers 69(10): 1500-1506 (2020) - [c6]Rezgar Sadeghi, Zainalabedin Navabi:
Built-In Predictors for Dynamic Crosstalk Avoidance. ETS 2020: 1-6 - [c5]Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi:
ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. VTS 2020: 1-6
2010 – 2019
- 2019
- [c4]Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi:
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ETS 2019: 1-6 - [c3]Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi:
Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. EWDTS 2019: 1-5 - [c2]Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi:
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS 2019: 1-6 - [c1]Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi:
An ESL Environment for Modeling Electrical Interconnect Faults. ISVLSI 2019: 88-93
Coauthor Index
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