Guest editorial - Masakazu Yamashina; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2002)

A low-power W-CDMA demodulator using specially-designed micro-DSPs - Hiroyuki Igura; Masaru Hirata; Junya Yamada; Masakazu Yamashina; Shigeru Ono (Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002, 2002)

Guest editorial - David B. Scott; Masakazu Yamashina (IEEE J. Solid State Circuits, 2001)

A Single-Chip Multiprocessor for Smart Terminals - Masato Edahiro; Satoshi Matsushita; Masakazu Yamashina; Naoki Nishi (IEEE Micro, 2000)

Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk - Masakazu Yamashina; Masato Motomura (Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, 2000)

Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI - Koichiro Furuta; Taro Fujii; Masato Motomura; Kazutoshi Wakabayashi; Masakazu Yamashina (Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000, 2000)

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller - Kazumasa Suzuki; Masayuki Daito; Tomoo Inoue; Kouhei Nadehara; Masahiro Nomura; Masayuki Mizuno; Tomofumi Iima; Shoichiro Sato; Terumi Fukuda; Tomohisa Arai; Ichiro Kuroda; Masakazu Yamashina (IEEE J. Solid State Circuits, 1999)

An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing - Hiroyuki Igura; Yukihiro Naito; Kenya Kazama; Ichiro Kuroda; Masato Motomura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1998)

An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration - Masato Motomura; Yoshiharu Aimoto; Atsufkni Shibayama; Yoshikazu Yabe; Masakazu Yamashina (6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, 1998)

A 0.25-\(μ\)m CMOS 0.9-V 100-MHz DSP core - Masanori Izumikawa; Hiroyuki Igura; Hitoshi Wakabayashi; Ken Nakajima; Tohru Mogami; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1997)

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking - Masayuki Mizuno; Yasushi Ooi; Naoya Hayashi; Junichi Goto; Masatoshi Hozumi; Koichiro Furuta; Atsufumi Shibayama; Yoetsu Nakazawa; Osamu Ohnishi; Shu-Yu Zhu; Yutaka Yokoyama; Yoichi Katayama; et al. (IEEE J. Solid State Circuits, 1997)

An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU - Yasushi Ooi; Osamu Ohnishi; Yutaka Yokoyama; Yoichi Katayama; Masayuki Mizuno; Masakazu Yamashina; Hideo Takano; Naoya Hayashi; Ichiro Tamitani (1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '97, Munich, Germany, April 21-24, 1997, 1997)

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI - Tomofumi lima; Masayuki Mizuno; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1996)

A current direction sense technique for multiport SRAM's - Masanori Izumikawa; Masakazu Yamashina (IEEE J. Solid State Circuits, 1996)

A GHz MOS adaptive pipeline technique using MOS current-mode logic - Masayuki Mizuno; Masakazu Yamashina; Koichiro Furuta; Hiroyuki Igura; Hitoshi Abiko; Kazuhiro Okabe; Atsuki Ono; Hachiro Yamada (IEEE J. Solid State Circuits, 1996)

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications - Tohru Kimura; Kazuyuki Nakamura; Yoshiharu Aimoto; Takashi Manabe; Nobuyuki Yamashita; Yoshihiro Fujita; Shin'ichiro Okazaki; Masakazu Yamashina (IEEE J. Solid State Circuits, 1995)

A 300-MHz 16-b 0.5-\(μ\)m BiCMOS digital signal processor core LSI - Masahiro Nomura; Masakazu Yamashina; Junichi Goto; Toshiaki Inoue; Kazumasa Suzuki; Masato Motomura; Youichi Koseki; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; Kouichi Kumagai; Tadayoshi Enomoto; et al. (IEEE J. Solid State Circuits, 1994)

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM - Nobuyuki Yamashita; Tohru Kimura; Yoshihiro Fujita; Yoshiharu Aimoto; Takashi Manabe; Shin'ichiro Okazaki; Kazuyuki Nakamura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1994)

A 500 MHz, 32 bit, 0.4 \(μ\)m CMOS RISC processor - Kazumasa Suzuki; Masakazu Yamashina; Takashi Nakayama; Masanori Izumikawa; Masahiro Nomura; Hiroyuki Igura; Hideki Heiuchi; Junichi Goto; Toshiaki Inoue; Youichi Koseki; Hitoshi Abiko; Kazuhiro Okabe; et al. (IEEE J. Solid State Circuits, 1994)

A 300-MHz 16-b BiCMOS video signal processor - Toshiaki Inoue; Junichi Goto; Masakazu Yamashina; Kazumasa Suzuki; Masahiro Nomura; Youichi Koseki; Tohru Kimura; Takao Atsumo; Masato Motomura; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; et al. (IEEE J. Solid State Circuits, 1993)

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI - Junichi Goto; Koichi Ando; Toshiaki Inoue; Masakazu Yamashina; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1991)

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI - Masakazu Yamashina; Junichi Goto; Fuyuki Okamoto; Koichi Ando; Hachiro Yamada; Tadahiko Horiuchi; Kimiko Nakamura; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1989)

A microprogrammable real-time video signal processor (VSP) for motion compensation - Masakazu Yamashina; Tadayoshi Enomoto; Takemitsu Kunio; Ichiro Tamitani; Hidenobu Harasaki; Yukio Endo; Takao Nishitani; Masao Satoh; Koichi Kikuchi (IEEE J. Solid State Circuits, 1988)