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2020 – today
- 2024
[j4]Xi Chen, Yitong Zhao
, An Guo, Jinwu Chen, Fangyuan Dong, Zhaoyang Zhang, Tianzhu Xiong, Bo Wang, Yuyao Kong, Xin Si:
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3181-3185 (2024)- [i1]Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu:
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. CoRR abs/2409.11418 (2024) - 2023
- [j3]Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang:
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. Sci. China Inf. Sci. 66(10) (2023) - [j2]Yuyao Kong, Xi Chen, Xin Si, Jun Yang:
Evaluation Platform of Time-Domain Computing-in-Memory Circuits. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1174-1178 (2023) - [c8]An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang:
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC 2023: 128-129 - [c7]Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang:
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. ISSCC 2023: 134-135 - 2022
- [c6]Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si:
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. ISCAS 2022: 3383-3387 - 2021
- [j1]Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin:
TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. IEEE J. Solid State Circuits 56(10): 3021-3038 (2021) - [c5]Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang:
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. ISOCC 2021: 195-196 - [c4]Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si:
Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices. UCET 2021: 47-52 - 2020
- [c3]Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin:
A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. A-SSCC 2020: 1-4
2010 – 2019
- 2019
- [c2]Yuyao Kong, Jun Yang:
In-memory Processing based on Time-domain Circuit. ACM Great Lakes Symposium on VLSI 2019: 435-438 - [c1]Jun Yang, Yuyao Kong, Zhen Wang, Yan Liu, Bo Wang, Shouyi Yin, Longxin Shi:
Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation. ISSCC 2019: 394-396
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