Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity. - Kam, Dongyun; Yun, Myeongji; Yoo, Sunwoo; Hong, Seungwoo; Zhang, Zhengya; Lee, Youngjoo (2025)

A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints. - Kim, Jaehee; Han, Sangil; Kam, Dongyun; Kong, Byeong Yong; Lee, Youngjoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications. - Park, Dain; Kam, Dongyun; Yun, Sangbu; Choe, Jeongwon; Lee, Youngjoo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Constrained Sorter Design using Zero-One Principle. - Han, Sangil; Kim, Jaehee; Kam, Dongyun; Kong, Byeong Yong; Kim, Mijung; Kim, Young-Seok; Lee, Youngjoo (2024)

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. - Kam, Dongyun; Yun, Sangbu; Choe, Jeongwon; Zhang, Zhengya; Lee, Namyoon; Lee, Youngjoo (2024)

Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity. - Kam, Dongyun; Yun, Myeongji; Yoo, Sunwoo; Hong, Seungwoo; Zhang, Zhengya; Lee, Youngjoo (CoRR, 2024)

Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations. - Kam, Dongyun; Kong, Byeong Yong; Lee, Youngjoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks. - Hwang, Ranggi; Kang, Minhoo; Lee, Jiwon; Kam, Dongyun; Lee, Youngjoo; Rhu, Minsoo (2023)

Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers. - Min, Jung Gyu; Kam, Dongyun; Byun, Younghoon; Park, Gunho; Lee, Youngjoo (2023)

Simplified Ordered Statistic Decoding for Short-Length Linear Block Codes. - Kim, Changhyeon; Kam, Dongyun; Kim, Seokki; Park, Giyoon; Lee, Youngjoo (IEEE Commun. Lett., 2022)

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm. - Hong, Seungwoo; Kam, Dongyun; Yun, Sangbu; Choe, Jeongwon; Lee, Namyoon; Lee, Youngjoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. - Kam, Dongyun; Min, Jung Gyu; Yoon, Jongho; Kim, Sunmean; Kang, Seokhyeong; Lee, Youngjoo (2022)

A 1.1μs 1.56Gb/s/mm2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology. - Kam, Dongyun; Kong, Byeong Yong; Lee, Youngjoo (2022)

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks. - Kang, Minhoo; Hwang, Ranggi; Lee, Jiwon; Kam, Dongyun; Lee, Youngjoo; Rhu, Minsoo (CoRR, 2022)

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism. - Kam, Dongyun; Yoo, Hoyoung; Lee, Youngjoo (IEEE Trans. Very Large Scale Integr. Syst., 2021)

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks. - Kim, Changhyeon; Rim, Dongyoung; Choe, Jeongwon; Kam, Dongyun; Park, Giyoon; Kim, Seokki; Lee, Youngjoo (2021)

Low-Latency Polar Decoder Using Overlapped SCL Processing. - Kam, Dongyun; Kong, Byeong Yong; Lee, Youngjoo (2021)

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. - Kam, Dongyun; Min, Jung Gyu; Yoon, Jongho; Kim, Sunmean; Kang, Seokhyeong; Lee, Youngjoo (CoRR, 2021)

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm. - Yun, Sangbu; Kam, Dongyun; Choe, Jeongwon; Kong, Byeong Yong; Lee, Youngjoo (2020)

Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance. - Moon, Seungsik; Kim, In-Soo; Kam, Dongyun; Jee, Dong-Woo; Choi, Junil; Lee, Youngjoo (IEEE Access, 2019)

Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications. - Kam, Dongyun; Lee, Youngjoo (2019)