16.4: SambaNova SN40L: A 5nm 2.5D Dataflow Accelerator with Three Memory Tiers for Trillion Parameter AI - Raghu Prabhakar; Junwei Zhou; Darshan Gandhi; Youngmoon Choi; Mahmood Khayatzadeh; Kyunglok Kim; Uma Durairajan; Jeongha Park; Satyajit Sarkar; Jinuk Luke Shin (IEEE International Solid-State Circuits Conference, ISSCC 2025, San Francisco, CA, USA, February 16-20, 2025, 2025)

AI SoC Design Challenges in the Foundation Model Era - Zhengyu Chen; Dawei Huang; Mingran Wang; Bowen Yang; Jinuk Luke Shin; Changran Hu; Bo Li; Raghu Prabhakar; Gao Deng; Yongning Sheng; Sihua Fu; Lu Yuan; et al. (IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, 2023)

SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0 - Raghu Prabhakar; Sumti Jairath; Jinuk Luke Shin (IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022, 2022)

Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference - Edith Beigné; Jinuk Luke Shin; Yusuke Oike; Chulwoo Kim; Jan Genoe (IEEE J. Solid State Circuits, 2016)

4.3 Fine-grained adaptive power management of the SPARC M7 processor - Venkatram Krishnaswamy; Jeffrey Brooks; Georgios K. Konstadinidis; Curtis McAllister; Ha Pham; Sebastian Turullols; Jinuk Luke Shin; Yifan YangGong; Haowei Zhang (2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, 2015)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, 2015)

Session 4 overview: Processors: High-performance digital subcommittee - Atsuki Inoue; Jinuk Luke Shin (2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, 2015)

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm - Jason Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Venkatram Krishnaswamy; Lance Kwong; Robert P. Masleid; et al. (IEEE J. Solid State Circuits, 2014)

Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor - Yifan YangGong; Sebastian Turullols; Daniel Woo; Changku Huang; King C. Yen; Venkatram Krishnaswamy; Kalon Holdbrook; Jinuk Luke Shin (IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014, 2014)

The Next Generation 64b SPARC Core in a T4 SoC Processor - Jinuk Luke Shin; Robert T. Golla; Hongping Penny Li; Sudesna Dash; Youngmoon Choi; Alan P. Smith; Harikaran Sathianathan; Mayur Joshi; Heechoul Park; Mohamed Elgebaly; Sebastian Turullols; Song Kim; et al. (IEEE J. Solid State Circuits, 2013)

3.6GHz 16-core SPARC SoC processor in 28nm - Jason Hart; Steve Butler; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Lance Kwong; Robert P. Masleid; et al. (2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, 2013)

Bandwidth and power management of glueless 8-socket SPARC T5 system - Venkatram Krishnaswamy; Dawei Huang; Sebastian Turullols; Jinuk Luke Shin (2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, 2013)

Session 3 overview: Processors: High performance digital subcommittee - Joshua Friedrich; Jinuk Luke Shin (2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, 2012)

The next-generation 64b SPARC core in a T4 SoC processor - Jinuk Luke Shin; Heechoul Park; Hongping Penny Li; Alan P. Smith; Youngmoon Choi; Harikaran Sathianathan; Sudesna Dash; Sebastian Turullols; Song Kim; Robert P. Masleid; Georgios K. Konstadinidis; Robert T. Golla; et al. (2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, 2012)

A 40 nm 16-Core 128-Thread SPARC SoC Processor - Jinuk Luke Shin; Dawei Huang; Bruce Petrick; Changku Hwang; Kenway W. Tam; Alan P. Smith; Ha Pham; Hongping Penny Li; Timothy Johnson; Francis Schumacher; Ana Sonia Leon; Allan Strong (IEEE J. Solid State Circuits, 2011)

A 40nm 16-core 128-thread CMT SPARC SoC processor - Jinuk Luke Shin; Kenway W. Tam; Dawei Huang; Bruce Petrick; Ha Pham; Changku Hwang; Hongping Penny Li; Alan P. Smith; Timothy Johnson; Francis Schumacher; David Greenhill; Ana Sonia Leon; et al. (IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, 2010)

A Power-Efficient High-Throughput 32-Thread SPARC Processor - Ana Sonia Leon; Kenway W. Tam; Jinuk Luke Shin; David Weisner; Francis Schumacher (IEEE J. Solid State Circuits, 2007)

The UltraSPARC T1 Processor: CMT Reliability - Ana Sonia Leon; Brian Langley; Jinuk Luke Shin (Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006, 2006)

A Power-Efficient High-Throughput 32-Thread SPARC Processor - Ana Sonia Leon; Jinuk Luke Shin; Kenway W. Tam; William Bryg; Francis Schumacher; Poonacha Kongetira; David Weisner; Allan Strong (2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, 2006)

A dual-core 64-bit ultraSPARC microprocessor for dense server applications - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Howard Levy; Ha Pham; Jinseung Son; Nathan Moon; Dina Bistry; Umesh Nair; Mandeep Singh; Vikas Mathur; et al. (IEEE J. Solid State Circuits, 2005)

Design and implementation of an embedded 512-KB level-2 cache subsystem - Jinuk Luke Shin; Bruce Petrick; Mandeep Singh; Ana Sonia Leon (IEEE J. Solid State Circuits, 2005)

Design and implementation of an embedded 512KB level 2 cache subsystem - Jinuk Luke Shin; Bruce Petrick; Howard Levy; Jinseung Son; Mandeep Singh; Vikas Mathur; Jung-Cheng Yeh; Heesung Choi; Vishal Gupta; Tom Ziaja; Ana Sonia Leon (Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004, 2004)

A dual-core 64b ultraSPARC microprocessor for dense server applications - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Ana Sonia Leon (Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, 2004)

Universal-V\(_dd\) 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell - Kenichi Osada; Jinuk Luke Shin; Masood Khan; Yude Liou; Karl Wang; Kenichi Shoji; Kenichi Kuroda; Shuji Ikeda; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2001)