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Antonio G. M. Strollo
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2020 – today
- 2024
- [c52]Ettore Napoli, Antonio G. M. Strollo, Efstratios Zacharelos, Gennaro Di Meo:
Comprehensive Analysis of Input Order Invariant Approximate 4-2 Compressors for Binary Multipliers. ISCAS 2024: 1-5 - [c51]Luca Tegazzini, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo:
Design of a Hardware-Efficient Floating-Point Multiplier with Dynamic Segmentation. PRIME 2024: 1-4 - 2023
- [j55]Efstratios Zacharelos
, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli:
Approximate squaring circuits exploiting recursive architectures. Integr. 91: 35-42 (2023) - [j54]Gennaro Di Meo
, Antonio Giuseppe Maria Strollo
, Davide De Caro
:
Novel Low-Power Floating-Point Divider With Linear Approximation and Minimum Mean Relative Error. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5275-5288 (2023) - [c50]Gerardo Saggese, Ettore Napoli, Antonio Giuseppe Maria Strollo:
CFPM: Run-time Configurable Floating-Point Multiplier. PRIME 2023: 173-176 - 2022
- [j53]Mauro D'Arco
, Ettore Napoli
, Efstratios Zacharelos
, Leopoldo Angrisani
, Antonio Giuseppe Maria Strollo:
Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs. Sensors 22(1): 234 (2022) - [j52]Gennaro Di Meo
, Davide De Caro
, Giacinto Paolo Saggese, Ettore Napoli
, Nicola Petra, Antonio Giuseppe Maria Strollo
:
A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 297-308 (2022) - [j51]Antonio Giuseppe Maria Strollo
, Ettore Napoli
, Davide De Caro
, Nicola Petra, Giacinto Paolo Saggese, Gennaro Di Meo
:
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2449-2462 (2022) - [j50]Efstratios Zacharelos
, Italo Nunziata
, Gerardo Saggese
, Antonio G. M. Strollo
, Ettore Napoli:
Approximate Recursive Multipliers Using Low Power Building Blocks. IEEE Trans. Emerg. Top. Comput. 10(3): 1315-1330 (2022) - [c49]Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli:
Approximate Recursive Multipliers Using Low Power Building Blocks. ARITH 2022: 67 - [c48]Italo Nunziata, Efstratios Zacharelos, Gerardo Saggese, Antonio Giuseppe Maria Strollo, Ettore Napoli:
Approximate Recursive Multipliers Using Carry Truncation and Error Compensation. PRIME 2022: 137-140 - [c47]Gennaro Di Meo
, Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section. PRIME 2022: 217-220 - [c46]Gerardo Saggese, Efstratios Zacharelos, Antonio Giuseppe Maria Strollo:
Low Power Spike Detector for Brain-Silicon Interface using Differential Amplitude Slope Operator. PRIME 2022: 301-304 - 2021
- [j49]Ettore Napoli
, Efstratios Zacharelos
, Mauro D'Arco
, Antonio Giuseppe Maria Strollo
:
Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4142-4155 (2021) - 2020
- [j48]Ettore Napoli
, Davide De Caro
, Nicola Petra, Antonio Giuseppe Maria Strollo
:
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 121-134 (2020) - [j47]Antonio Giuseppe Maria Strollo
, Ettore Napoli
, Davide De Caro
, Nicola Petra, Gennaro Di Meo
:
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3021-3034 (2020) - [j46]Davide De Caro
, Gennaro Di Meo
, Ettore Napoli
, Nicola Petra, Antonio Giuseppe Maria Strollo
:
A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications. IEEE Trans. Circuits Syst. 67-I(11): 3839-3852 (2020) - [c45]Gennaro Di Meo
, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo:
Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding. ICECS 2020: 1-4 - [c44]Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. ISCAS 2020: 1 - [c43]Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra, Gennaro Di Meo:
Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j45]Gerardo Castellano, Davide De Caro, Darjn Esposito
, Paolo Bifulco, Ettore Napoli, Nicola Petra, Emilio Andreozzi
, Mario Cesarelli, Antonio G. M. Strollo:
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy. Circuits Syst. Signal Process. 38(7): 3269-3294 (2019) - [j44]Darjn Esposito
, Davide De Caro
, Gennaro Di Meo
, Ettore Napoli
, Antonio G. M. Strollo
:
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic. Circuits Syst. Signal Process. 38(12): 5606-5622 (2019) - [c42]Gennaro Di Meo
, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo:
Variable-Rounded LMS Filter for Low-Power Applications. ApplePies 2019: 155-161 - 2018
- [j43]Daniele Montanari, Gerardo Castellano, Ehsan Kargaran, Giacomo Pini, Saheed Tijani, Davide De Caro
, Antonio Giuseppe Maria Strollo, Danilo Manstretta, Rinaldo Castello:
An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands. IEEE J. Solid State Circuits 53(7): 1945-1959 (2018) - [j42]Michele De Martino
, Davide De Caro
, Darjn Esposito
, Ettore Napoli
, Nicola Petra, Antonio Giuseppe Maria Strollo
:
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3885-3896 (2018) - [j41]Darjn Esposito
, Antonio Giuseppe Maria Strollo
, Ettore Napoli
, Davide De Caro
, Nicola Petra:
Approximate Multipliers Based on New Approximate Compressors. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4169-4182 (2018) - [c41]Darjn Esposito, Gennaro Di Meo
, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli:
Design of Low-Power Approximate LMS Filters with Precision-Scalability. ApplePies 2018: 237-243 - [c40]Darjn Esposito, Gennaro Di Meo
, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli:
Quality-Scalable Approximate LMS Filter. ICECS 2018: 849-852 - [c39]Antonio G. M. Strollo, Darjn Esposito:
Approximate computing in the nanoscale era. ICICDT 2018: 21-24 - [c38]Darjn Esposito, Gennaro Di Meo
, Davide De Caro, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo:
On the Use of Approximate Multipliers in LMS Adaptive Filters. ISCAS 2018: 1-5 - [c37]Darjn Esposito, Gennaro Di Meo
, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo:
Stall-Aware Fixed-Point Implementation of LMS Filters. PRIME 2018: 169-172 - 2017
- [j40]Davide De Caro
, Fabio Tessitore, Gianfranco Vai, Gerardo Castellano, Ettore Napoli, Nicola Petra, Claudio Parrella, Antonio G. M. Strollo:
Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines. Circuits Syst. Signal Process. 36(4): 1341-1360 (2017) - [j39]Ettore Napoli
, Gerardo Castellano, Davide De Caro, Darjn Esposito
, Nicola Petra, Antonio G. M. Strollo:
A SISO Register Circuit Tailored for Input Data with Low Transition Probability. IEEE Trans. Computers 66(1): 45-51 (2017) - [j38]Ettore Napoli
, Gerardo Castellano, Davide De Caro
, Darjn Esposito
, Nicola Petra, Antonio Giuseppe Maria Strollo:
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1040-1050 (2017) - [j37]Davide De Caro, Ettore Napoli, Darjn Esposito
, Gerardo Castellano, Nicola Petra, Antonio G. M. Strollo:
Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1187-1200 (2017) - [j36]Gerardo Castellano, Daniele Montanari, Davide De Caro, Danilo Manstretta, Antonio Giuseppe Maria Strollo:
An Efficient Digital Background Control for Hybrid Transformer-Based Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(12): 3068-3080 (2017) - [c36]Darjn Esposito
, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo:
On the use of approximate adders in carry-save multiplier-accumulators. ISCAS 2017: 1-4 - [c35]Darjn Esposito
, Antonio G. M. Strollo, Massimo Alioto:
Power-precision scalable latch memories. ISCAS 2017: 1-4 - 2016
- [j35]Darjn Esposito
, Davide De Caro, Antonio Giuseppe Maria Strollo:
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1200-1209 (2016) - [c34]Gerardo Castellano, Davide De Caro, Antonio G. M. Strollo, Danilo Manstretta
:
A low power control system for real-time tuning of a hybrid transformer-based receiver. ICECS 2016: 328-331 - [c33]Darjn Esposito
, Gerardo Castellano, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo:
Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs. ISCAS 2016: 1970-1973 - [c32]Ettore Napoli, Gerardo Castellano, Darjn Esposito
, Antonio G. M. Strollo:
Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence. LASCAS 2016: 23-26 - 2015
- [j34]Mariangela Genovese, Paolo Bifulco, Davide De Caro
, Ettore Napoli, Nicola Petra
, Maria Romano, Mario Cesarelli
, Antonio G. M. Strollo:
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. Integr. 49: 114-124 (2015) - [j33]Davide De Caro
, Fabio Tessitore, Gianfranco Vai, Nicola Imperato, Nicola Petra, Ettore Napoli, Claudio Parrella, Antonio G. M. Strollo:
A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS. IEEE J. Solid State Circuits 50(9): 2074-2089 (2015) - [j32]Darjn Esposito
, Davide De Caro
, Ettore Napoli, Nicola Petra
, Antonio Giuseppe Maria Strollo:
Variable Latency Speculative Han-Carlson Adder. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1353-1361 (2015) - [c31]Giorgio Lopez, Ettore Napoli, Domenico Meglio, Antonio G. M. Strollo:
An FPGA processor for real-time, fixed-point refinement of CDVS keypoints. ISCAS 2015: 2832-2835 - [c30]Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo:
FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage. LASCAS 2015: 1-4 - 2014
- [j31]Mariangela Genovese, Ettore Napoli, Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo:
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA. Integr. 47(2): 261-271 (2014) - [j30]Nicola Petra
, Davide De Caro
, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo:
Truncated squarer with minimum mean-square error. Microelectron. J. 45(6): 799-804 (2014) - [j29]Davide De Caro
, Mariangela Genovese, Ettore Napoli, Nicola Petra
, Antonio G. M. Strollo:
Accurate Fixed-Point Logarithmic Converter. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 526-530 (2014) - [j28]Alessandro Cilardo, Davide De Caro
, Nicola Petra
, Francesco Caserta, Nicola Mazzocca
, Ettore Napoli, Antonio Giuseppe Maria Strollo:
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3426-3435 (2014) - [c29]Davide De Caro, Michele De Martino, Nicola Petra, Antonio G. M. Strollo:
Analysis of Spread-Spectrum Clocking Modulations Under Synchronization Timing Constraint. ApplePies 2014: 153-159 - [c28]Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo:
Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering. ApplePies 2014: 161-167 - [c27]Ettore Napoli, Mauro D'Arco
, Pasquale Di Cosmo, Mariangela Genovese, Antonio G. M. Strollo:
FPGA based system for the generation of noise with programmable power spectrum. ISCAS 2014: 1300-1303 - [c26]Giorgio Lopez, Ettore Napoli, Antonio G. M. Strollo:
A Frequency Domain Processor for Real-Time CDVS Keypoints Extraction. SITIS 2014: 94-98 - 2013
- [j27]Mariangela Genovese
, Ettore Napoli
, Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo:
FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video. J. Electr. Comput. Eng. 2013: 129589:1-129589:8 (2013) - [j26]Ashkan Ashrafi
, Antonio G. M. Strollo
, Oscar Gustafsson
:
Hardware Implementation of Digital Signal Processing Algorithms. J. Electr. Comput. Eng. 2013: 782575:1-782575:2 (2013) - [j25]Nicola Petra
, Sebastiano Russo, Davide De Caro
, Ettore Napoli, Giancarlo Barbarino
, Antonio G. M. Strollo
:
NORA based TDC in 90 nm CMOS. Microelectron. J. 44(6): 489-495 (2013) - [j24]Davide De Caro
, Nicola Petra
, Antonio Giuseppe Maria Strollo
, Fabio Tessitore, Ettore Napoli:
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2375-2388 (2013) - 2011
- [j23]Antonio G. M. Strollo
, Davide De Caro
, Nicola Petra
:
Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations. IEEE Trans. Computers 60(3): 418-432 (2011) - [j22]Nicola Petra
, Davide De Caro
, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
:
Design of Fixed-Width Multipliers With Linear Compensation Function. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 947-960 (2011) - [j21]Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo
:
Efficient Logarithmic Converters for Digital Signal Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 667-671 (2011) - [j20]Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo
:
Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(10): 2409-2419 (2011) - 2010
- [j19]Davide De Caro
, Carlo Alberto Romani, Nicola Petra
, Antonio G. M. Strollo
, Claudio Parrella:
A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS. IEEE J. Solid State Circuits 45(5): 1048-1060 (2010) - [j18]Nicola Petra
, Davide De Caro
, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo
:
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1312-1325 (2010) - [c25]Davide De Caro
, Marino Coppola
, Nicola Petra
, Ettore Napoli, Antonio G. M. Strollo
, Valeria Garofalo:
High-speed differential resistor ladder for A/D converters. ISCAS 2010: 1723-1726 - [c24]Nicola Petra
, Davide De Caro
, Antonio G. M. Strollo
, Valeria Garofalo, Ettore Napoli, Marino Coppola
, Pietro Todisco:
Fixed-width CSD multipliers with minimum mean square error. ISCAS 2010: 4149-4152 - [c23]Valeria Garofalo, Marino Coppola
, Davide De Caro
, Ettore Napoli, Nicola Petra
, Antonio G. M. Strollo
:
A novel truncated squarer with linear compensation function. ISCAS 2010: 4157-4160
2000 – 2009
- 2009
- [j17]Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo
:
Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 364-373 (2009) - [j16]Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo
:
High-Performance Special Function Unit for Programmable 3-D Graphics Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1968-1978 (2009) - 2008
- [j15]Andrea Bonfanti
, Davide De Caro
, Alfio Dario Grasso
, Salvatore Pennisi
, Carlo Samori
, Antonio G. M. Strollo
:
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS. IEEE J. Solid State Circuits 43(6): 1403-1413 (2008) - [j14]Antonio Giuseppe Maria Strollo
, Davide De Caro
, Nicola Petra
:
A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 µm CMOS. IEEE J. Solid State Circuits 43(11): 2503-2513 (2008) - [j13]Paolo Pulici, Antonio Girardi, Gian Pietro Vanalli, Roberto Izzi, Giacomo Bernardi, Giancarlo Ripamonti
, Antonio G. M. Strollo
, Giovanni Campardo:
A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1921-1928 (2008) - [j12]Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo
:
Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 2116-2127 (2008) - [c22]Valeria Garofalo, Nicola Petra
, Davide De Caro
, Antonio G. M. Strollo
, Ettore Napoli:
Low error truncated multipliers for DSP applications. ICECS 2008: 29-32 - [c21]Antonio G. M. Strollo
, Davide De Caro
, Nicola Petra
, Ettore Napoli, Valeria Garofalo:
Constrained piecewise polinomial approximation for hardware implementation of elementary functions. ICECS 2008: 698-701 - [c20]Davide De Caro
, Nicola Petra
, Antonio G. M. Strollo
:
A high performance floating-point special function unit using constrained piecewise quadratic approximation. ISCAS 2008: 472-475 - 2007
- [j11]Davide De Caro
, Nicola Petra
, Antonio Giuseppe Maria Strollo
:
A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 µm CMOS. IEEE J. Solid State Circuits 42(1): 151-160 (2007) - [j10]Antonio Giuseppe Maria Strollo
, Davide De Caro
, Nicola Petra
:
A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique. IEEE J. Solid State Circuits 42(2): 350-360 (2007) - [j9]Nicola Petra
, Davide De Caro
, Antonio G. M. Strollo
:
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme. IEEE Trans. Computers 56(11): 1470-1483 (2007) - [c19]Nicola Petra
, Davide De Caro
, Antonio G. M. Strollo
:
Design of fixed-width multipliers with minimum mean square error. ECCTD 2007: 464-467 - [c18]Nicola Petra
, Davide De Caro
, Antonio G. M. Strollo
:
High Speed Galois Fields GF(2m) Multipliers. ECCTD 2007: 468-471 - [c17]Valeria Garofalo, Ettore Napoli, Nicola Petra
, Antonio Giuseppe Maria Strollo
:
Code compression for ARM7 embedded systems. ECCTD 2007: 687-690 - 2006
- [c16]Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOS. ISSCC 2006: 972-981 - [c15]Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOS. ISSCC 2006: 982-991 - 2005
- [j8]Davide De Caro
, Antonio Giuseppe Maria Strollo
:
High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation. IEEE J. Solid State Circuits 40(11): 2220-2227 (2005) - [j7]Davide De Caro
, Antonio G. M. Strollo
:
High-performance direct digital frequency synthesizers using piecewise-polynomial approximation. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(2): 324-337 (2005) - [j6]Antonio G. M. Strollo
, Nicola Petra
, Davide De Caro
:
Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers. IEEE Trans. Circuits Syst. II Express Briefs 52-II(8): 501-507 (2005) - [j5]Antonio G. M. Strollo
, Davide De Caro
, Ettore Napoli, Nicola Petra
:
A novel high-speed sense-amplifier-based flip-flop. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1266-1274 (2005) - [c14]Davide De Caro
, Ettore Napoli, Nicola Petra
, Antonio G. M. Strollo
:
A high-speed sense-amplifier based flip-flop. ECCTD 2005: 99-102 - 2004
- [j4]Davide De Caro
, Ettore Napoli, Antonio G. M. Strollo
:
Direct digital frequency synthesizers with polynomial hyperfolding technique. IEEE Trans. Circuits Syst. II Express Briefs 51-II(7): 337-344 (2004) - [c13]Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra:
High-speed direct digital frequency synthesizers in 0.25-μm CMOS. CICC 2004: 163-166 - [c12]Antonio Giuseppe Maria Strollo, Nicola Petra, Davide De Caro, Ettore Napoli:
An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS. ESSCIRC 2004: 479-482 - 2003
- [j3]Antonio G. M. Strollo
, Davide De Caro
:
Direct digital frequency synthesizers exploiting piecewise linear Chebyshev approximation. Microelectron. J. 34(11): 1099-1106 (2003) - [j2]Antonio G. M. Strollo
, Davide De Caro
:
Booth folding encoding for high performance squarer circuits. IEEE Trans. Circuits Syst. II Express Briefs 50(5): 250-254 (2003) - [c11]Antonio Giuseppe Maria Strollo, Davide De Caro
, Ettore Napoli, Nicola Petra:
Direct digital frequency synthesis with dual-slope approach. ESSCIRC 2003: 397-400 - [c10]Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca
, Antonio G. M. Strollo:
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. FPL 2003: 292-302 - 2002
- [c9]Beniamino Di Martino, Nicola Mazzocca
, Giacinto Paolo Saggese, Antonio G. M. Strollo:
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. FPL 2002: 47-58 - [c8]Davide De Caro
, Ettore Napoli, Antonio G. M. Strollo
:
ROM-less direct digital frequency synthesizers exploiting polynomial approximation. ICECS 2002: 481-484 - [c7]Giacinto Paolo Saggese, Antonio G. M. Strollo
, Nicola Mazzocca
, Davide De Caro
:
Shuffled serial adder: an area-latency effective serial adder. ICECS 2002: 607-610 - 2001
- [c6]Antonio G. M. Strollo, Ettore Napoli, Davide De Caro:
New design of squarer circuits using Booth encoding and folding techniques. ICECS 2001: 193-196 - [c5]Antonio G. M. Strollo, Ettore Napoli, Davide De Caro, Giacinto Paolo Saggese:
A reconfigurable 2D convolver for real-time SAR imaging. ICECS 2001: 741-744 - [c4]Davide De Caro, Nicola Mazzocca, Ettore Napoli, Giacinto Paolo Saggese, Antonio G. M. Strollo:
Test pattern generator for hybrid testing of combinational circuits. ICECS 2001: 745-748 - 2000
- [j1]Antonio G. M. Strollo
, Ettore Napoli, Carlo Cimino:
Analysis of power dissipation in double edge-triggered flip-flops. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 624-629 (2000) - [c3]Antonio G. M. Strollo, Ettore Napoli, Davide De Caro:
New clock-gating techniques for low-power flip-flops. ISLPED 2000: 114-119
1990 – 1999
- 1999
- [c2]Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli:
Power dissipation in one-latch and two-latch double edge triggered flip-flops. ICECS 1999: 1419-1422 - [c1]Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino:
A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing. ICECS 1999: 1631-1634
Coauthor Index
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