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2010 – 2019
- 2012
[j26]Thierry Paillat, Gérard Touchard, Yves Bertrand:
"Capacitive Sensor" to Measure Flow Electrification and Prevent Electrostatic Hazards. Sensors 12(11): 14315-14326 (2012)
2000 – 2009
- 2009
- [j25]Sébastien Horna
, Daniel Méneveaux, Guillaume Damiand, Yves Bertrand:
Consistency constraints and 3D building reconstruction. Comput. Aided Des. 41(1): 13-27 (2009) - [j24]Beatrice Pradarelli, Laurent Latorre, Marie-Lise Flottes, Yves Bertrand, Pascal Nouet:
Remote Labs for Industrial IC Testing. IEEE Trans. Learn. Technol. 2(4): 304-311 (2009) - [c64]Florence Azaïs, Yves Bertrand, Michel Renovell:
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS 2009: 158-163 - 2008
- [c63]Fabien Soulier, Lionel Gouyet, Guy Cathébras, Serge Bernard, David Guiraud, Yves Bertrand:
Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition. BIOSTEC (Selected Papers) 2008: 148-159 - [c62]Fabien Soulier, Lionel Gouyet, Guy Cathébras, Serge Bernard, David Guiraud, Yves Bertrand:
Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection. BIODEVICES (2) 2008: 180-185 - [c61]Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell:
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS 2008: 233-238 - 2007
- [c60]Mehdi Baba-ali, David Marcheix, Xavier Skapin, Yves Bertrand:
Generic computation of bulletin boards into geometric kernels. Afrigraph 2007: 85-93 - [c59]Sébastien Horna, Guillaume Damiand, Daniel Méneveaux, Yves Bertrand:
Building 3D indoor scenes topology from 2D architectural plans. GRAPP (GM/R) 2007: 37-44 - [c58]Serge Bernard, Lionel Gouyet, Guy Cathébras, Fabien Soulier, David Guiraud, Yves Bertrand:
Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection. ICECS 2007: 74-77 - 2005
- [j23]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electron. Test. 21(3): 291-298 (2005) - [j22]Sylvain Brandel, Sébastien Schneider, Michel Perrin, Nicolas Guiard, Jean-François Rainaud, Pascal Lienhardt, Yves Bertrand:
Automatic Building of Structured Geological Models. J. Comput. Inf. Sci. Eng. 5(2): 138-148 (2005) - [j21]Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand:
Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005) - [j20]Sylvain Prat, Patrick Gioia, Yves Bertrand, Daniel Méneveaux:
Connectivity compression in an arbitrary dimension. Vis. Comput. 21(8-10): 876-885 (2005) - [c57]Laurent Latorre, Yves Bertrand, Michel Robert, Marie-Lise Flottes:
Test Engineering Education in Europe - The CRTC experience through the EuNICE-Test project. EDUTECH 2005: 63-77 - 2004
- [j19]Guillaume Damiand, Yves Bertrand, Christophe Fiorio:
Topological model for two-dimensional image representation: definition and optimal extraction algorithm. Comput. Vis. Image Underst. 93(2): 111-154 (2004) - [j18]Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electron. Test. 20(3): 257-267 (2004) - [j17]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electron. Test. 20(4): 375-387 (2004) - [c56]Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich:
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA 2004: 135-139 - [c55]Jean-Denis Techer, Serge Bernard, Yves Bertrand, Guy Cathébras, David Guiraud:
New implantable stimulator for the FES of paralyzed muscles. ESSCIRC 2004: 455-458 - [c54]Sylvain Brandel, Sébastien Schneider, Michel Perrin, Nicolas Guiard, Jean-François Rainaud, Pascal Lienhardt, Yves Bertrand:
Automatic building of structured geological models. Symposium on Solid Modeling and Applications 2004: 59-69 - 2003
- [j16]Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei:
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Des. Test Comput. 20(1): 60-67 (2003) - [j15]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. 19(4): 377-386 (2003) - [j14]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electron. Test. 19(4): 469-479 (2003) - [j13]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
A-to-D converters static error detection from dynamic parameter measurement. Microelectron. J. 34(10): 945-953 (2003) - [c53]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173 - [c52]Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
A New Methodology For ADC Test Flow Optimization. ITC 2003: 201-209 - [c51]Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden:
Test Engineering Education in Europe: the EuNICE-Test Project. MSE 2003: 85-86 - 2002
- [j12]Michel Renovell, Florence Azaïs, Yves Bertrand:
Improving Defect Detection in Static-Voltage Testing. IEEE Des. Test Comput. 19(6): 83-89 (2002) - [j11]Franck Ledoux, Jean-Marc Mota, Agnès Arnould, Catherine Dubois, Pascale Le Gall, Yves Bertrand:
Spécifications formelles du chanfreinage. Tech. Sci. Informatiques 21(8): 1073-1098 (2002) - [c50]Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems. DATE 2002: 1120 - [c49]Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival:
European Network for Test Education. DELTA 2002: 230-234 - [c48]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling gate oxide short defects in CMOS minimum transistors. ETW 2002: 15-20 - [c47]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
A high accuracy triangle-wave signal generator for on-chip ADC testing. ETW 2002: 89-94 - [c46]Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
Testing Resonant Micro-Electro-Mechanical Sensors using the Oscillation-based Test Methodology. LATW 2002: 99-104 - [c45]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski:
Estimating Static Parameters of A-to-D Converters from Spectral Analysis. LATW 2002: 174-179 - [c44]Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. VTS 2002: 439-444 - 2001
- [j10]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electron. Test. 17(2): 139-147 (2001) - [j9]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electron. Test. 17(3-4): 255-266 (2001) - [j8]Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
Test and Testability of a Monolithic MEMS for Magnetic Field Sensing. J. Electron. Test. 17(5): 439-450 (2001) - [j7]André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand:
On the detectability of CMOS floating gate transistor faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 116-128 (2001) - [c43]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
Implementation of a linear histogram BIST for ADCs. DATE 2001: 590-595 - [c42]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Analog BIST Generator for ADC Testing. DFT 2001: 338-346 - [c41]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436 - [c40]Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing. VLSI-SOC 2001: 461-472 - [c39]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048 - [c38]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. LATW 2001: 112-117 - [c37]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW 2001: 266-272 - [c36]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS 2001: 266-271 - [c35]Franck Ledoux, Agnès Arnould, Pascale Le Gall, Yves Bertrand:
Geometric Modelling with CASL. WADT 2001: 176-200 - [c34]Sylvain Thery, Dominique Bechmann, Yves Bertrand:
N-Dimensional Gregory-Bezier for N-Dimensional Cellular Complexes. WSCG (Short Papers) 2001: 16-23 - 2000
- [j6]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electron. Test. 16(3): 259-267 (2000) - [j5]Sylvain Brandel, Dominique Bechmann, Yves Bertrand:
Thickening: an operation for animation. Comput. Animat. Virtual Worlds 11(5): 261-277 (2000) - [j4]Jean Françon, Yves Bertrand:
Topological 3D-manifolds: a statistical study of the cells. Theor. Comput. Sci. 234(1-2): 233-254 (2000) - [c33]Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium 2000: 78-83 - [c32]Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-230 - [c31]Yves Bertrand, Guillaume Damiand, Christophe Fiorio:
Topological Encoding of 3D Segmented Images. DGCI 2000: 311-324 - [c30]Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs:
On the Temperature Dependencies of Analog BIST. LATW 2000: 88-93 - [c29]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters. LATW 2000: 118-122 - [c28]Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand:
Hardware Resource Minimization for Histogram-Based ADC BIST. VTS 2000: 247-254
1990 – 1999
- 1999
- [j3]Michel Renovell, Florence Azaïs, Yves Bertrand:
Detection of Defects Using Fault Model Oriented Test Sequences. J. Electron. Test. 14(1-2): 13-22 (1999) - [c27]Laurent Latorre, Yves Bertrand, P. Hazard, Francis Pressecq, Pascal Nouet:
Design, Characterization & Modelling of a CMOS Magnetic Field Sensor. DATE 1999: 239-243 - [c26]Yves Bertrand, Christophe Fiorio, Yann Pennaneach:
Border Map: A Topological Representation for nD Image Analysis. DGCI 1999: 242-257 - [c25]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Functional and structural testing of switched-current circuits. ETW 1999: 22-27 - [c24]Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults. ITC 1999: 477-486 - [c23]Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival:
A Successful Distance-Learning Experience for IC Test Education. MSE 1999: 20-21 - 1998
- [c22]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
BISTing Switched-Current Circuits. Asian Test Symposium 1998: 372-377 - [c21]Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387 - [c20]Michel Renovell, Florence Azaïs, Yves Bertrand:
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE 1998: 815-821 - [c19]Sylvain Brandel, Dominique Bechmann, Yves Bertrand:
STIGMA: a 4-dimensional modeller for animation. Computer Animation and Simulation 1998: 103-126 - [c18]Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand:
A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. SBCCI 1998: 175-178 - [c17]Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin:
Design-For-Testability for Switched-Current Circuits. VTS 1998: 370-375 - 1997
- [j2]Dominique Bechmann, Yves Bertrand, Sylvain Thery:
Continuous free form deformation. Comput. Networks ISDN Syst. 29(14): 1715-1725 (1997) - [c16]A. Dargelas, C. Gauthron, Yves Bertrand:
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. ED&TC 1997: 29-36 - [c15]Michel Renovell, Florence Azaïs, Yves Bertrand:
On-chip analog output response compaction. ED&TC 1997: 568-572 - [c14]Michel Renovell, Yves Bertrand:
Test Strategy Sensitivity to Defect Parameters. ITC 1997: 607-616 - 1996
- [c13]Michel Renovell, P. Huc, Yves Bertrand:
The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. EDCC 1996: 205-213 - [c12]Michel Renovell, Florence Azaïs, Yves Bertrand:
The multi-configuration: A DFT technique for analog circuits. VTS 1996: 54-59 - [c11]Michel Renovell, P. Huc, Yves Bertrand:
Bridging fault coverage improvement by power supply control. VTS 1996: 338-343 - 1995
- [c10]Michel Renovell, P. Huc, Yves Bertrand:
Serial transistor network modeling for bridging fault simulation. Asian Test Symposium 1995: 100-106 - [c9]Michel Renovell, Florence Azaïs, Yves Bertrand:
A design-for-test technique for multistage analog circuits. Asian Test Symposium 1995: 113-119 - [c8]S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault:
Test configurations to enhance the testability of sequential circuits. Asian Test Symposium 1995: 160-168 - [c7]Michel Renovell, P. Huc, Yves Bertrand:
The concept of resistance interval: a new parametric model for realistic resistive bridging fault. VTS 1995: 184-189 - 1994
- [j1]Yves Bertrand, Jean-François Dufourd:
Algebraic Specification of a 3D-Modeler Based on Hypermaps. CVGIP Graph. Model. Image Process. 56(1): 29-60 (1994) - [c6]Michel Renovell, P. Huc, Yves Bertrand:
The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. EDCC 1994: 165-177 - [c5]Michel Renovell, P. Huc, Yves Bertrand:
CMOS bridging fault modeling. VTS 1994: 392-397 - 1993
- [c4]Yves Bertrand, Frédéric Bancel, Michel Renovell:
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC 1993: 989-997 - [c3]Yves Bertrand, Jean-François Dufourd, Jean Françon, Pascal Lienhardt:
Algebraic Specification and Development in Geometric Modeling. TAPSOFT 1993: 75-89 - [c2]Yves Bertrand, Frédéric Bancel, Michel Renovell:
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design 1993: 51-54 - 1992
- [c1]Michel Renovell, M. Ildevert, Yves Bertrand:
A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs. VLSI Design 1992: 352-353
Coauthor Index
[c64] [c61] [j23] [j21] [j18] [j17] [j16] [j15] [j14] [j13] [c53] [c52] [j12] [c48] [c47] [c45] [j10] [j9] [j7] [c43] [c42] [c41] [c39] [c38] [c37] [c36] [j6] [c33] [c32] [c30] [c29] [c28] [j3] [c25] [c24] [c22] [c21] [c20] [c18] [c17] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c2] [c1]
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