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Dae-Han Kwon
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2020 – today
- 2023
- [j4]Dae-Han Kwon, Seongju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dongyoon Ka, Kyu-Dong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Guhyun Kim, Byeongju An, Jaewook Lee, Donguc Ko, Younggun Jun, Ilwoong Kim, Choungki Song, Ilkon Kim, Chanwook Park, Seho Kim, Chunseok Jeong, Euicheol Lim, Dongkyun Kim, Jieun Jang, Il Park, Junhyun Chun, Joohwan Cho:
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application. IEEE J. Solid State Circuits 58(1): 291-302 (2023) - 2022
- [j3]Dongsuk Kang, Jae-Woo Park, Injae Park, Minsu Park, Xuefan Jin, Kyu-Dong Hwang, Dae-Han Kwon, Jung-Hoon Chun:
A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer. IEEE J. Solid State Circuits 57(10): 3083-3093 (2022) - [j2]Soyeong Shin, Yongjae Lee, Jiheon Park, Jihyo Kang, Kyunghoon Kim, Dae-Han Kwon, Sangkwon Lee, Jieun Jang, Joo-Hwan Cho, Deog-Kyoon Jeong:
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 814-818 (2022) - [c4]Seong Ju Lee, Kyu-Young Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dong Yoon Ka, Kyu-Dong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Donguc Ko, Younggun Jun, Keewon Cho, Ilwoong Kim, Choungki Song, Chunseok Jeong, Dae-Han Kwon, Jieun Jang, Il Park, Junhyun Chun, Joohwan Cho:
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. ISSCC 2022: 1-3 - 2021
- [c3]Jae-Woo Park, Dongsuk Kang, Injae Park, Minsu Park, Xuefan Jin, Kyu-Dong Hwang, Dae-Han Kwon, Jung-Hoon Chun:
A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer. A-SSCC 2021: 1-3
2010 – 2019
- 2018
- [c2]Kyu-Dong Hwang, Boram Kim, Sang-Yeon Byeon, Kyu-Young Kim, Dae-Han Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-Young Jang, Seung-Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee:
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications. ISSCC 2018: 210-212 - 2016
- [j1]Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi, Young Jae Jang, Hae-Kang Jung, Kyunghoon Kim, Dae-Han Kwon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 51(8): 1890-1901 (2016) - 2012
- [c1]Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim:
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC 2012: 48-50
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