Ka-Band CMOS Power Amplifier Using Stacked Structure With Cascode-Like Operation - Taehun Kim; Hayeon Jeong; Seong-Jin Jang; Jaeyong Lee; Changkun Park (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Design of CMOS-Based Unit Channel of Beamforming Transceivers for FACS Applications - Seong-Jin Jang; Hui Dong Lee; Bonghyuk Park; Seunghyun Jang; Sunwoo Kong; Changkun Park (IEEE Access, 2023)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking - Young-Ju Kim; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim; Sukhyun Lim; et al. (IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, 2019)

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2018)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM - Joung-Wook Moon; Hye-Sung Yoo; Hundai Choi; Il-Won Park; Seok-Yong Kang; Jun-Bae Kim; Haeyoung Chung; Kiho Kim; Dong-Hun Lee; Ki-Jae Song; Seok-Hun Hyun; Indal Song; et al. (IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, 2018)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking - Young-Ju Kim; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, 2018)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, 2018)

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process - Jin-Hyeok Baek; Chang-Kyo Lee; Kiho Kim; Daesik Moon; Gil-Hoon Cha; Jin-Seok Heo; Min-Su Ahn; Dong-Ju Kim; Jae-Joon Song; Seokhong Kwon; Jongmin Kim; Kyung-Soo Kim; et al. (2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, 2018)

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (IEEE J. Solid State Circuits, 2017)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim; et al. (IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017, 2017)

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices - Sang-uhn Cha; Seongil O; Hyunsung Shin; Sangjoon Hwang; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Gyo-Young Jin; Young Hoon Son; Hyunyoon Cho; Jung Ho Ahn; Nam Sung Kim (2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017, 2017)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, 2017)

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices - Hye-Jung Kwon; Eunsung Seo; ChangYong Lee; Young-Hun Seo; Gong-Heum Han; Hye-Ran Kim; Jong-Ho Lee; Min-Su Jang; Sung-Geun Do; Seung-Hyun Cho; Jae-Koo Park; Su-Yeon Doo; et al. (2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, 2017)

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, 2017)

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM) - Hyunui Lee; Sukyong Kang; Hye-Seung Yu; Won-Joo Yun; Jae-Hun Jung; Sungoh Ahn; Wang-Soo Kim; Beomyong Kil; Yoo-Chang Sung; Sang-Hoon Shin; Yong-Sik Park; Yong-Hwan Kim; et al. (IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016, 2016)

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution - Hye-Yoon Joo; Seung-Jun Bae; Young-Soo Sohn; Young-Sik Kim; Kyung-Soo Ha; Min-Su Ahn; Young-Ju Kim; Yong-Jun Kim; Ju-Hwan Kim; Won-Jun Choi; Chang-Ho Shin; Soo Hwan Kim; et al. (2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, 2016)

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, 2016)

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme - Il-Min Yi; Seung-Jun Bae; Min-Kyun Chae; Soo-Min Lee; Young Jae Jang; Young-Chul Cho; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, 2016)

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation - Tae-Young Oh; Hoeju Chung; Jun-Young Park; Ki-Won Lee; Seung-Hoon Oh; Su-Yeon Doo; Hyoung-Joo Kim; ChangYong Lee; Hye-Ran Kim; Jong-Ho Lee; Jin-Il Lee; Kyung-Soo Ha; et al. (IEEE J. Solid State Circuits, 2015)

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM - Yarui Peng; Bon Woong Ku; Youn-Sik Park; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Sung Kyu Lim (Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015)

5.7 A 29nW bandgap reference circuit - Jongmi Lee; Youngwoo Ji; Seungnam Choi; Young-Chul Cho; Seong-Jin Jang; Joo-Sun Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, 2015)

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs - Won-Joo Yun; Indal Song; Hanki Jeoung; Hundai Choi; Seok-Ho Lee; Jun-Bae Kim; Chi-Wook Kim; Jung-Hwan Choi; Seong-Jin Jang; Joo-Sun Choi (2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, 2015)

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface - Chang-Kyo Lee; Min-Su Ahn; Daesik Moon; Kiho Kim; Yoon-Joo Eom; Won-Young Lee; Jongmin Kim; Sanghyuk Yoon; Baekkyu Choi; Seokhong Kwon; Joon-Young Park; Seung-Jun Bae; et al. (Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015, 2015)

Development of the knocking decision system using the CKP signal collection and analysis - Hwa-seon Kim; Seong-Jin Jang; Jong-Wook Jang (Int. J. Secur. Networks, 2014)

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs - Reum Oh; Byunghyun Lee; Sang-Woong Shin; Wonil Bae; Hundai Choi; Indal Song; Yun-Sang Lee; Jung-Hwan Choi; Chi-Wook Kim; Seong-Jin Jang; Joo-Sun Choi (Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014, 2014)

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Seok-Hun Hyun; Hanki Jeoung; Ki Won Lee; Jun-Seok Park; et al. (IEEE J. Solid State Circuits, 2013)

A Study on Knocking Analysis Simulator Based on CRDI Engine ECU - Hwa-seon Kim; Seong-Jin Jang; Jong-Wook Jang (Computer Applications for Graphics, Grid Computing, and Industrial Environment - International Conferences, GDC, IESH and CGAG 2012, Held as Part of the Future Generation Information Technology Conference, FGIT 2012, Gangneug, Korea, December 16-19, 2012. Proceedings, 2012)

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Hanki Jeoung; Ki Won Lee; Junsuk Park; Jongeun Lee; et al. (2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, 2012)

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Satoru Yamada; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (IEICE Trans. Electron., 2011)

A Study on Dynamic Gateway System for MOST GATEWAY Scheduling Algorithm - Seong-Jin Jang; Jong-Wook Jang (Advanced Communication and Networking - Third International Conference, ACN 2011, Brno, Czech Republic, August 15-17, 2011. Proceedings, 2011)

A study on scheduling algorithm for optimization of traffic distribution in MOST GATEWAY - Seong-Jin Jang; Jong-Wook Jang (IEEE 17th Asia-Pacific Conference on Communications, APCC 2011, Sabah, Malaysia, October 2-5, 2011, 2011)

A Study on Dynamic Gateway System for MOST GATEWAY Scheduling Algorithm in MOST25 and MOST150 Networks - Seong-Jin Jang; Jong-Wook Jang (Convergence and Hybrid Information Technology - 5th International Conference, ICHIT 2011, Daejeon, Korea, September 22-24, 2011. Proceedings, 2011)

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010, 2010)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques - Seung-Jun Bae; Young-Soo Sohn; Kwang-Il Park; Kyoung-Ho Kim; Dae-Hyun Chung; Jingook Kim; Si-Hong Kim; Min-Sang Park; Jae-Hyung Lee; Sam-Young Bang; Ho-Kyung Lee; In-Soo Park; et al. (2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, 2008)

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007, 2007)

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control - Sang-Bo Lee; Seong-Jin Jang; Jin-Seok Kwak; Sang-Jun Hwang; Young-Hyun Jun; Soo-In Cho; Chil-Gee Lee (IEEE J. Solid State Circuits, 2005)

A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM - Young-Hyun Jun; Weon-Hwa Jeong; Jong-Hoon Park; Tae-Hoon Kim; Seong-Wook Kim; Jae-Sik Lee; Seong-Jin Jang; Chang-Man Khang; Hee-Gook Lee (1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, 1993)