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Fahad Bin Muslim
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2020 – today
- 2024
- [j8]Fahad Bin Muslim, Kashif Inayat, Safiullah Khan:
LPCHISEL: Automatic power intent generation for a chisel-based ASIC design. Comput. Electr. Eng. 115: 109115 (2024) - [j7]Safiullah Khan, Kashif Inayat, Fahad Bin Muslim, Yasir Ali Shah, Muhammad Atif Ur Rehman, Ayesha Khalid, Malik Imran, Akmalbek Abdusalomov:
Securing the IoT ecosystem: ASIC-based hardware realization of Ascon lightweight cipher. Int. J. Inf. Sec. 23(6): 3653-3664 (2024) - 2023
- [j6]Kashif Inayat, Fahad Bin Muslim, Javed Iqbal, Syed Agha Hassnain Mohsan, Hend Khalid Alkahtani, Samih Mohemmed Mostafa:
Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration. Sensors 23(9): 4297 (2023) - 2020
- [j5]Azhar Ul-Haq, Marium Jalal, Muhammad Aamir, Carlo Cecati, Fahad Bin Muslim, Arsalan Ahmad Raja, Javed Iqbal:
Simulations and experimental validation of one cycle controlled nine-level inverter using FPGA. Comput. Electr. Eng. 88: 106885 (2020) - [j4]Ali Zahir, Shadan Khan Khattak, Anees Ullah, Pedro Reviriego, Fahad Bin Muslim, Waleed Ahmad:
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2726-2730 (2020) - [i1]S. M. Usman Hashmi, Muntazir Hussain, Fahad Bin Muslim, Kashif Inayat, Seong Oun Hwang:
Implementation of Symbol Timing Recovery for Estimation of Clock Skew. CoRR abs/2006.14413 (2020)
2010 – 2019
- 2017
- [b1]Fahad Bin Muslim:
Energy-efficient hardware design based on high-level synthesis. Polytechnic University of Turin, Italy, 2017 - [j3]Fahad Bin Muslim, Liang Ma, Mehdi Roozmeh, Luciano Lavagno:
Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis. IEEE Access 5: 2747-2762 (2017) - [j2]Affaq Qamar, Fahad Bin Muslim, Francesco Gregoretti, Luciano Lavagno, Mihai Teodor Lazarescu:
High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze? IEEE Access 5: 8419-8432 (2017) - [j1]Affaq Qamar, Fahad Bin Muslim, Javed Iqbal, Luciano Lavagno:
LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow. Microprocess. Microsystems 50: 26-38 (2017) - 2016
- [c4]Liang Ma, Fahad Bin Muslim, Luciano Lavagno:
High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis. EMS 2016: 157-162 - [c3]Fahad Bin Muslim, Alexandros Demian, Liang Ma, Luciano Lavagno, Affaq Qamar:
Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL. FedCSIS (Position Papers) 2016: 141-145 - 2015
- [c2]Fahad Bin Muslim, Affaq Qamar, Luciano Lavagno:
Low power methodology for an ASIC design flow based on high-level synthesis. SoftCOM 2015: 11-15 - [c1]Affaq Qamar, Fahad Bin Muslim, Luciano Lavagno:
Analysis and Implementation of the Semi-Global Matching 3D Vision Algorithm Using Code Transformations and High-Level Synthesis. VTC Spring 2015: 1-5
Coauthor Index
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last updated on 2024-10-25 20:15 CEST by the dblp team
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